ZipRecruiter

Log In

1

Physical Verification Jobs (NOW HIRING)

Apple

GPU Physical Verification Design Engineer

Austin, TX · On-site

$134K - $138K/yr

You will be realizing the complete physical design verification closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration.

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC. Description • As a member of our physical design team, you will perform various ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC. Description • As a member of our physical design team, you will perform various ...

Apple

SoC Physical Design Verification Engineer

Beaverton, OR · On-site

$141K - $145K/yr

In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC. Description • As a member of our physical design team, you will perform various ...

previous pagenext page

Showing results 21-40

All JobsPhysical Verification Jobs

Physical Verification information

See salary details

$12

$18

$26

How much do physical verification jobs pay per hour?

As of Sep 13, 2026, the average hourly pay for physical verification in the United States is $18.87, according to ZipRecruiter salary data. Most workers in this role earn between $16.35 and $20.19 per hour, depending on experience, location, and employer.

What is physical verification in the context of semiconductor design?

Physical verification is the process of checking a semiconductor chip's layout against design rules and verifying that the layout will function as intended when manufactured. This step ensures that the design meets foundry requirements for manufacturability, reliability, and performance. Physical verification includes checks like Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checking (ERC). It is a critical step before tape-out to avoid costly manufacturing errors.

What are the key skills and qualifications needed to thrive as a physical verification engineer, and why are they important?

To thrive as a Physical Verification Engineer, you need a solid understanding of semiconductor design, layout verification, and a degree in electrical engineering or a related field. Familiarity with EDA tools such as Calibre or Mentor Graphics, and knowledge of DRC/LVS checks, are typically required. Attention to detail, problem-solving abilities, and strong teamwork skills help engineers effectively identify and resolve design issues. These competencies are crucial for ensuring integrated circuits meet design specifications and function reliably in production.

What are some common challenges faced during physical verification in semiconductor design, and how can they be addressed?

Physical verification engineers often encounter challenges such as complex design rule violations, lengthy verification runtimes, and tight project deadlines. Addressing these requires a strong understanding of EDA tools (like Calibre or Pegasus), good communication with design and layout teams to clarify specifications, and proactive debugging skills to quickly resolve issues. Leveraging automation scripts and regularly running incremental checks can also help identify errors early and streamline the process. Collaboration and continuous learning are key to navigating these challenges effectively.

What is the difference between Physical Verification vs Physical Auditor?

AspectPhysical VerificationPhysical Auditor
CertificationsTypically requires certifications like Certified Physical Verification SpecialistRequires similar certifications, often with additional auditing credentials
Work EnvironmentOn-site inspections, physical checks at locationsOn-site and office-based audits, review of verification processes
Employer & Industry UsageUsed by telecom, real estate, and asset management companiesEngaged by auditing firms, regulatory bodies, and large corporations
Search & Comparison IntentUnderstanding physical verification processesComparing verification with auditing roles

Physical Verification involves on-site checks to confirm assets or data, while Physical Auditor performs comprehensive audits of verification processes and records. Both roles require similar certifications and are used across industries like telecom and real estate, but their focus differs: verification is about confirming physical assets, whereas auditing reviews procedures and compliance.

More about Physical Verification jobs

What cities are hiring for Physical Verification jobs?

Cities with the most Physical Verification job openings:

What states have the most Physical Verification jobs?

States with the most job openings for Physical Verification jobs include:

What job categories do people searching Physical Verification jobs look for?

The top searched job categories for Physical Verification jobs are:

What other helpful pages are available for Physical Verification?

Other pages related to Physical Verification:

Physical Verification jobs near you
Infographic showing various Physical Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 17% Part Time, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $39,247 per year, or $18.9 per hour.

SoC Physical Verification Engineer, HBM

Folsom, CA • On-site

Micron Technology
Semiconductor and Electronic Component Manufacturing • 10K+ employees
Learn more about Micron Technologyexternal

$97K - $205K/yr

Full-time

Medical, Dental, Vision, PTO

Re-posted 4 days ago

Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

Job description

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next-generation HBM logic die and memory-centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry-leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints. This role combines full-chip physical verification ownership - including DRC, LVS, ERC, and DFM - with deep collaboration across implementation and silicon bring-up, ensuring design integrity from layout through first silicon.
Responsibilities will include, but are not limited to:
  • Implement physical verification sign-off for full-chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM).
  • Implement and debug foundry-qualified rule decks, manage waivers, and drive clean closure while ensuring compliance with advanced-node foundry requirements.
  • Perform reliability verification across multiple power domains, including electrostatic discharge (ESD), latch-up, electromigration, floating nets, and connectivity checks.
  • Run density, metal fill, and chemical mechanical polishing (CMP) checks to ensure yield-aware manufacturability at 3 nanometer and below.
  • Perform parasitic resistance-capacitance (RC) extraction and support correlation of physical verification results with post-silicon measurements.
  • Develop, maintain, and optimize physical verification flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting languages.
  • Drive adoption of machine learning (ML) and artificial intelligence (AI)-based physical verification and power-performance-area (PPA) optimization tools.
  • Partner with physical design, custom layout, computer-aided design (CAD), register-transfer level (RTL), product engineering, EDA, and foundry teams, including direct collaborate with TSMC, from design kick-off through tape-out readiness and sign-off decision gates.
  • Demonstrating AI to develop AI assisted development workflows.

Minimum Qualifications:
  • Experience with full-chip or block-level physical verification for advanced-node system-on-chip, memory, or heterogeneous integration designs.
  • Experience in physical verification methodologies, including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
  • Experience using industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
  • Working knowledge of full RTL-to-GDS implementation flows, including place-and-route, extraction, and their impact on physical verification outcomes.
  • Ability to drive verification closure by maintaining strong communication with multi-functional teams in a global engineering environment.
  • Proficiency with demonstrating AI and AI-enabled development workflows.

Preferred Qualifications:
  • Experience with high-bandwidth memory (HBM), DRAM, or memory-centric system-on-chip physical verification, including multi-die, chiplet, or 2.5D/3D integration.
  • Background in GPU, CPU, or high-performance accelerator physical implementation at advanced process nodes with aggressive sign-off and tape-out schedules.
  • Familiarity with foundry develop rule documents, front-end-of-line (FEOL) and back-end-of-line (BEOL) rules, and advanced develop for manufacturability guidelines.
  • Exposure to post-silicon failure analysis, yield learning, or layout-based debug with correlation between physical verification results and silicon behavior.
  • Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience, with 2 or more years of relevant industry experience.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$97,000.00 - $205,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

What Micron Technology employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply