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Physical Design Jobs in California (NOW HIRING)

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Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is okay C2C Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Apple Inc.

Physical Design Engineer

Sunnyvale, CA · On-site

$184.70 - $324.80/hr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

New

Apple

Physical Design Engineer

Cupertino, CA

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Bodega Bay, CA

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

DensityAI

Physical Design Engineer

Mountain View, CA · On-site

$160K - $165K/yr

About the role Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from ...

Apple Inc.

Physical Design Engineer

Cupertino, CA · On-site

$129.30 - $225.30/hr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies.

Apple

Physical Design Engineer

Cupertino, CA

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Apple

Physical Design Engineer

Bodega Bay, CA

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies.

Stellent IT LLC

Physical Design Engineer.

San Diego, CA · On-site

$144K - $148K/yr

Hello, Tittle-Physical Design Engineer Location- San Diego, California, San Jose, CA and Irvine, CA Job Type- Fulltime Physical Design Engineer We are looking for humble geniuses, who believe that ...

DensityAI

Physical Design Engineer

Mountain View, CA

$230K - $400K/yr

About the role Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from ...

DensityAI

Physical Design Engineer

Mountain View, CA · On-site

$230K - $400K/yr

About the role Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from ...

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Showing results 21-40

All JobsPhysical Design JobsPhysical Design Jobs in California

Physical Design information

See California salary details

$93.8K

$139.6K

How much do physical design jobs pay per year?

As of Aug 8, 2026, the average yearly pay for physical design in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What is physical design in the context of electronics and semiconductors?

Physical design refers to the process of transforming a circuit's logical representation into a geometrical layout that can be manufactured on a semiconductor chip. This involves placing and routing the various components, such as transistors and interconnections, while meeting performance, power, and area constraints. Physical design engineers use specialized software tools to optimize the layout and ensure it adheres to manufacturing rules. The process is a critical step in the development of integrated circuits (ICs) and directly impacts the chip’s speed, power consumption, and size.

What are the key skills and qualifications needed to thrive as a physical design engineer, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, digital circuit design, and VLSI concepts, usually supported by a relevant degree. Proficiency with EDA tools like Cadence, Synopsys, or Mentor Graphics, as well as familiarity with scripting languages (e.g., TCL, Perl), is essential. Strong problem-solving, attention to detail, and effective communication skills help you address complex design challenges and collaborate within cross-functional teams. These competencies are crucial for optimizing chip layouts, ensuring manufacturability, and meeting performance and timing requirements in semiconductor development.

What are some common challenges faced by physical design engineers in meeting timing closure during chip development?

Physical Design engineers often encounter challenges in achieving timing closure due to factors such as increasing circuit complexity, tight power and area constraints, and process variations. Meeting timing goals requires careful floorplanning, placement, and routing, as well as close collaboration with logic design and verification teams to resolve critical path issues. Engineers must also frequently iterate designs and use advanced EDA tools to optimize performance while balancing trade-offs between speed, power, and manufacturability.

How to get into physical design?

To enter physical design, candidates typically need a bachelor's degree in electrical engineering, computer engineering, or a related field. Gaining experience with hardware description languages like VHDL or Verilog, and proficiency in EDA tools such as Synopsys or Cadence, is essential. Internships or entry-level positions in chip design can also provide valuable practical experience.

What is the difference between Physical Design vs Logic Design?

AspectPhysical DesignLogic Design
Primary FocusTranslating logical circuits into physical layoutsCreating logical circuit schematics and functional specifications
Skills RequiredEDA tools, layout constraints, circuit optimizationHardware description languages, digital logic, circuit theory
Work EnvironmentASIC/FPGA design teams, semiconductor companiesDesign teams, electronic design automation (EDA) environments
CertificationsTypically none specific, but EDA tool proficiency is valuedHardware description language certifications (e.g., VHDL, Verilog)

Physical Design and Logic Design are closely related stages in chip development. Logic Design focuses on creating the logical circuit functions, while Physical Design involves implementing those functions into physical layouts on silicon. Both roles require knowledge of digital circuits, but Physical Design emphasizes layout optimization and tool proficiency, whereas Logic Design centers on circuit behavior and description.

What are the most commonly searched types of Physical Design jobs in California? The most popular types of Physical Design jobs in California are:
What are popular job titles related to Physical Design jobs in California? For Physical Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Physical Design jobs in California look for? The top searched job categories for Physical Design jobs in California are:
What cities in California are hiring for Physical Design jobs? Cities in California with the most Physical Design job openings:
Physical Design jobs near you
Infographic showing various Physical Design job openings in California as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 19% Part Time, 1% Temporary, 2% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

Physical Design Engineer

search-tactics

San Jose, CA • On-site

$70 - $80/hr

Contractor

Posted 9 days ago

Job description

Position: Physical Design Engineer
Location: San Jose, CA Hybrid

Duration: 12 Months

VISA: H-1, GC, USC is okay C2C

Position Overview

We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams.

Key Responsibilities

Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.

Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing.

Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.

Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.

Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.

Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.

5+ years of experience in ASIC or SoC Physical Design.

Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.

Experience working on large, high-performance semiconductor designs with demanding timing requirements.

Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.

Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.

Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.

Preferred Qualifications

Experience supporting complex SoC, AI, HPC, or accelerator designs.

Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.

Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.

Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.