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Physical Design Engineer Internship Jobs in California

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Altera

Physical Design Engineer

San Jose, CA

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Apple

Physical Design Engineer

Cupertino, CA

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

AIT Global, Inc.

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Job Title: Physical Design Engineer Location: San Francisco, CA (Bay Area) * Good understanding of Cadence tools (Innovous, Quantus, Voltus). (Must) * Deep knowledge about industry standards in ...

New

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$133 - $193/hr

Physical Design Engineer** to join our Silicon Engineering and Physical Design organization. In this role, you will be responsible for implementing advanced custom IP and SoC designs from RTL through ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Etched

Physical Design Engineer

Cupertino, CA · On-site

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Socionext US

Physical Design Engineer

Milpitas, CA · On-site

$195K - $220K/yr

Physical Design Engineer - Socionext America, Milpitas Description Socionext Inc. (SNI) is an innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide.

Etched

Physical Design Engineer

Cupertino, CA · On-site

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Apple

Physical Design Engineer

Bodega Bay, CA · On-site

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role We are seeking a Physical Design Engineer to join our Silicon Design Automation & Implementation organization. In this role, you will contribute to the implementation of custom IP and ...

Apple Inc.

Physical Design Engineer

Sunnyvale, CA · On-site

$184.70 - $324.80/hr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Apple

Physical Design Engineer

Bodega Bay, CA

$262K - $394K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple Inc.

Physical Design Engineer

Cupertino, CA · On-site

$129.30 - $225.30/hr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Bodega Bay, CA · On-site

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

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All JobsPhysical Design Engineer JobsPhysical Design Engineer Internship JobsPhysical Design Engineer Internship Jobs in California

Physical Design Engineer Internship information

What is a physical design engineer internship?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What do physical design engineer interns do?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.

What are the key skills and qualifications needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

What are the most commonly searched types of Physical Design Engineer jobs in California?

The most popular types of Physical Design Engineer jobs in California are:

What are popular job titles related to Physical Design Engineer Internship jobs in California?

For Physical Design Engineer Internship jobs in California, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Internship jobs in California look for?

The top searched job categories for Physical Design Engineer Internship jobs in California are:

What cities in California are hiring for Physical Design Engineer Internship jobs?

Cities in California with the most Physical Design Engineer Internship job openings:

Physical Design Engineer Internship jobs near you
Infographic showing various Physical Design Engineer Internship job openings in California as of August 2026, with employment types broken down into 6% Internship, 65% Full Time, and 29% Contract. Highlights an 100% In-person job distribution.

Physical Design Engineer

Altera Corporation

San Jose, CA • On-site

$118K - $169K/yr

Full-time

Re-posted 23 days ago

Job description

Job Details:
Job Description:
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from netlist through physical implementation and sign-off. You will be responsible for executing physical design tasks at the block and subsystem level, helping optimize designs for performance, power, and area (PPA) while meeting quality and schedule requirements.
You will collaborate with design, architecture, DFT, CAD/EDA, and other engineering teams to resolve implementation challenges and support successful design delivery. This is an opportunity to develop your expertise in physical design and gain exposure to the unique implementation requirements of advanced FPGA technologies.
Key Responsibilities
  • Execute physical design implementation activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction, and physical design sign-off for assigned blocks or subsystems.
  • Analyze and optimize designs for timing, power, and area (PPA) to meet project requirements.
  • Perform static timing analysis and timing closure, identify critical paths, and work with design teams to resolve timing issues.
  • Review and debug physical implementation issues related to placement, congestion, clocking, routing, timing, and design constraints.
  • Support physical verification activities including DRC, LVS, and related sign-off checks and help resolve identified issues.
  • Work with RTL, architecture, DFT, CAD/EDA, and other engineering teams to understand design requirements and resolve physical implementation challenges.
  • Apply established physical design methodologies and flows using industry-standard EDA tools.
  • Develop basic scripts or automation, using Tcl, Python, Perl, Shell, or similar languages, to improve productivity and automate repetitive physical design tasks.
  • Support block-level integration activities, including physical constraints, pin placement, timing constraints, and interface requirements.
  • Participate in design reviews, documentation, and continuous improvement of physical design processes and methodologies.
  • Contribute to successful tape-out by completing assigned implementation tasks and resolving physical design issues within established project schedules.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$118,900 - $169,895 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Qualifications:
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 4+ years of industry experience in physical design, physical implementation, or SoC/ASIC backend design, including:
  • 4+ years of hands-on experience with digital ASIC and/or SoC physical design, including exposure to floorplanning, placement, clock tree synthesis (CTS), routing, ECO implementation, and physical sign-off.
  • Experience using industry-standard EDA physical design and sign-off tools such as Synopsys IC Compiler II, Fusion Compiler, PrimeTime, Cadence Innovus, or equivalent tools.
  • Experience with static timing analysis and timing closure, including analyzing timing reports and helping resolve setup and hold violations.
  • Experience working with physical design constraints, including clocks, timing constraints, placement constraints, and design rules.
  • Experience debugging common physical implementation issues such as timing violations, congestion, routing issues, and design rule violations.
  • Familiarity with physical verification activities including DRC, LVS, and related physical sign-off checks.
  • Ability to work effectively with RTL design, architecture, DFT, CAD/EDA, and other engineering teams throughout the physical implementation process.
  • Basic scripting or automation experience using Tcl, Python, Perl, Shell, or similar programming languages is preferred.
  • Understanding of semiconductor physical design concepts including power planning, placement, clocking, routing, timing closure, and physical verification.

Preferred Qualifications
  • Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • Experience with advanced semiconductor process technologies such as 16nm, 10nm, 7nm, 5nm, or below.
  • Experience with FPGA or programmable logic device physical implementation.
  • Familiarity with FPGA architectures, including programmable logic, routing fabrics, configurable logic blocks, I/O structures, and on-chip interconnect.
  • Experience with full-chip or hierarchical physical implementation flows.
  • Experience with low-power physical design concepts such as clock gating, power domains, power intent, or power-aware implementation.
  • Experience with physical design automation or scripting using Tcl, Python, Perl, or Shell.
  • Familiarity with power integrity concepts such as IR drop, electromigration (EM), and signal integrity.
  • Exposure to physical design sign-off methodologies and manufacturing considerations.
  • Experience working in a collaborative, cross-functional semiconductor engineering environment.
  • Exposure to AI/ML-assisted physical design optimization tools or methodologies is a plus.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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