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Physical Design Engineer Intern Jobs in Tempe, AZ

Intel

Silicon Packaging Design Engineer

Phoenix, AZ

$135K/yr

Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and ... Engineering, or a STEM related field Experience listed above should be in the following:

Intel

RTL Design Engineer

Phoenix, AZ

$105.65K - $200.34K/yr

... for physical implementation. Reviews the verification plan and implementation to ensure design ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...

MASTER HW LOCHNER INC

Airport Design Engineer

Mesa, AZ · On-site

Design of airport engineering projects including runways, taxiways, aprons, airfield lighting ... Wellness Program for Physical and Mental Health * Lochner Cares Non-Profit 501c3 * Education and ...

Lochner

Airport Design Engineer

Mesa, AZ · On-site +1

Design of airport engineering projects including runways, taxiways, aprons, airfield lighting ... Wellness Program for Physical and Mental Health * Lochner Cares Non-Profit 501c3 * Education and ...

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How much do physical design engineer intern jobs pay per hour?

As of May 27, 2026, the average hourly pay for physical design engineer intern in Tempe, AZ is $18.50, according to ZipRecruiter salary data. Most workers in this role earn between $15.43 and $20.05 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a Physical Design Engineer Intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What does a Physical Design Engineer Intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are popular job titles related to Physical Design Engineer Intern jobs in Tempe, AZ? For Physical Design Engineer Intern jobs in Tempe, AZ, the most frequently searched job titles are:
What job categories do people searching Physical Design Engineer Intern jobs in Tempe, AZ look for? The top searched job categories for Physical Design Engineer Intern jobs in Tempe, AZ are:
What cities near Tempe, AZ are hiring for Physical Design Engineer Intern jobs? Cities near Tempe, AZ with the most Physical Design Engineer Intern job openings:
Physical Design Engineer Intern jobs near you
Silicon Packaging Design Engineer

Silicon Packaging Design Engineer

Intel

Phoenix, AZ

$135K/yr

Full-time

Medical, Retirement, PTO

Posted yesterday

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:Job Description: 

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving the end-to-end development of silicon interposer and bridge designs that define the future of computing and connectivity. As a key contributor to Intel's cutting-edge technology, you will play a pivotal role in bridging silicon and hardware design, optimizing package performance, and delivering high-impact solutions that meet performance, cost, and manufacturability goals. Your expertise will directly contribute to Intel's mission to create world-changing technology that improves lives and connects communities worldwide.
Key Responsibilities:


- Design and implement physical layout and routing of silicon interposers and embedded bridges.
- Perform substrate fit and routing studies to evaluate design tradeoffs in performance, cost, and manufacturability.
- Collaborate closely with silicon, technology development and hardware teams to optimize system-level design, including silicon-package-board integration and pinout.
- Propose design updates changes for rules and conduct internal and external reviews to ensure design feasibility.
- Analyze design data and resolve design rule checks (DRCs) to achieve optimized and manufacturable package designs.
- Utilize industry-leading electronic design automation (EDA) tools, including Virtuoso, Innovus, FusionCompiler, ICvalidator, and Calibre, to create robust package layouts.
- Document processes and design specifications in the product lifecycle management system to ensure traceability and efficient collaboration.
- Conduct reviews with partner teams to close milestone requirements

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:


- Bachelor's degree with 3+ years of experience OR Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM related field

Experience listed above should be in the following:

  • Proficiency in custom layout and Auto-place-and-route EDA tools including Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or Calibre.
  • Experience with silicon physical layout design and development, routing interconnects, and/or review tools.

Additionally, the candidate should have at least one of the following:

  • 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals.
  • 1+ year of experience of Power Distribution and power integrity assessments.
  • 1+ year of experience of reliability requirements for interconnects.


Preferred Qualifications:

  • Familiarity with industry-leading silicon physical design methodologies and workflows.
  • Ability to effectively collaborate across multi-disciplinary teams and communicate technical concepts clearly.
  • A passion for innovation, problem-solving, and continuous improvement in a fast-paced environment.
  • Prior experience in optimizing silicon performance and conducting tradeoff studies for advanced packaging designs.

Join Intel and become an integral part of shaping tomorrow's technology today. Apply now to seize the opportunity to innovate, lead, and create meaningful impact on a global scale

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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