Role: Analog and RF layout engineer Work location: Sunnyvale, CA Job Type: Contract Interview: Phone/Skype • Minimum 6+ years of experience in Analog and RF layout. • Experience developing and ...
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Pddn information
What is the difference between Pddn vs Data Analyst?
| Aspect | Pddn | Data Analyst |
|---|---|---|
| Required Credentials | Typically a diploma or associate degree in a related field | Bachelor's degree in statistics, mathematics, or related field |
| Work Environment | Office settings, data processing centers | Office environments, often collaborating with various departments |
| Employer & Industry Usage | Used in logistics, manufacturing, and supply chain sectors | Common across finance, marketing, healthcare, and tech industries |
| Common Search & Comparison | Often compared for entry-level data roles | Compared for analytical and data processing positions |
The main difference between Pddn and Data Analyst lies in their typical educational requirements and industry usage. Pddn roles are more focused on data processing with a diploma or associate degree, mainly in logistics or manufacturing. Data Analysts usually hold a bachelor's degree and work across diverse industries analyzing data to support decision-making. Both roles involve working with data, but their scope and industry focus differ significantly.
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Job description
Job Description
Role: Analog and RF layout engineer
Work location: Sunnyvale, CA
Job Type: Contract
Interview: Phone/Skype
Job Description:
• Minimum 6+ years of experience in Analog and RF layout.
• Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level.
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs.
• Experience with floor planning, block level routing and top-level chip assemble.
• Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.
Key Responsibilities:
developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level
What are the Mandatory skills and skill proficiencies required for this position?
advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
What are the Optional skills and skill proficiencies for this position?
Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.
All your information will be kept confidential according to EEO guidelines.
About PDDN
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Fremont, CA, US
Year founded
2004