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Part Time Remote Asic Physical Design Engineer Jobs

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their ... This is a fully remote, part-time engagement requiring approximately 20-40 hours per week ...

Air Aviation LLC

Manufacturing Engineer

San Jose, CA · Remote

$85K - $110K/yr

... part-time remote contract basis. The Manufacturing Engineer will be responsible for applying engineering principles to assist in the design, development, and evaluation of mechanical systems and ...

Rohadfox Construction Control Services Corp.

Be Seen First

Cost Estimator-Part-Time Remote

Miami, FL · Remote

This is a Remote Part-time opportunity requiring occasional visits to the work site(s) in Florida ... Engineering Design services. Established in 1976, Rohadfox is one of the oldest minority owned ...

Implicit

AI Engineer (US-Based / Part-Time)

Applied AI Engineer (Part-Time, Remote - U.S.) Innovation is at the heart of what we do. At ... Design and build AI applications powered by LLMs, RAG, semantic search, and AI agents. * Develop ...

Implicit

AI Engineer (US-Based / Part-Time)

Applied AI Engineer (Part-Time, Remote - U.S.) Innovation is at the heart of what we do. At ... Design and build AI applications powered by LLMs, RAG, semantic search, and AI agents. * Develop ...

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Part Time Remote Asic Physical Design Engineer information

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$95K

$141.5K

How much do part time remote asic physical design engineer jobs pay per year?

As of Sep 3, 2026, the average yearly pay for part time remote asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a part time remote ASIC Physical Design Engineer?

Part time remote ASIC Physical Design Engineers are professionals who work on designing the physical layout of Application-Specific Integrated Circuits (ASICs) while working remotely and on a part-time schedule. Their responsibilities typically include tasks such as floorplanning, placement, routing, timing analysis, and verification of chip designs. These engineers use specialized Electronic Design Automation (EDA) tools to ensure that the ASIC meets performance, power, and area requirements. Working remotely allows them to collaborate with global teams, while the part-time nature of the job offers flexibility in working hours.

How does working part-time and remotely as an ASIC Physical Design Engineer impact collaboration with the broader engineering team?

As a part-time remote ASIC Physical Design Engineer, effective communication and proactive collaboration are essential. You'll often coordinate with cross-functional teams—including verification, logic design, and DFT engineers—through virtual meetings and collaborative tools. While remote work offers flexibility, it also requires strong organizational skills to manage overlapping schedules and ensure alignment on project milestones. Many companies address these challenges by adopting agile methodologies, regular check-ins, and clear documentation practices to keep everyone on the same page.

What are the key skills and qualifications needed to thrive as a part time remote ASIC Physical Design Engineer, and why are they important?

To thrive as a Part Time Remote ASIC Physical Design Engineer, you need a solid understanding of digital design principles, experience with ASIC flow, and a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and familiarity with scripting languages like TCL or Python, is typically required. Strong problem-solving skills, effective communication, and the ability to work independently make someone stand out in this role. These skills and qualities are essential for delivering high-quality designs, collaborating with distributed teams, and adhering to project timelines in a remote setting.

What is the difference between Part Time Remote Asic Physical Design Engineer vs Part Time Remote Digital IC Design Engineer?

AspectPart Time Remote Asic Physical Design EngineerPart Time Remote Digital IC Design Engineer
Required SkillsPhysical design, layout, verification, EDA toolsDigital logic design, RTL coding, simulation, synthesis
Work EnvironmentDesign implementation, layout, physical verificationRTL coding, functional verification, logic design
Industry UsageSemiconductor companies, chip design firmsSemiconductor, electronics, and integrated circuit companies

Both roles are common in the semiconductor industry and often require knowledge of EDA tools. The Physical Design Engineer focuses on the physical implementation of chips, while the Digital IC Design Engineer emphasizes digital logic design and RTL coding. They share similar work environments but differ in their core responsibilities.

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Part Time Remote Asic Physical Design Engineer jobs near you
Infographic showing various Part Time Remote Asic Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 74% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

ASIC/SoC Design & Verification Engineer

Weekday AI

Remote

$70 - $100/hr

Part-time

This job post has expired today. Applications are no longer accepted.

Job description

This role is for one of our clients
Compensation: $70-$100 per hour
Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.
Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.
This is a fully remote, part-time engagement requiring approximately 20-40 hours per week, depending on your availability.
Requirements
Key Responsibilities
  • Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
  • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
  • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
  • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
  • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
  • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.
Required Qualifications
  • Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
  • Strong proficiency in SystemVerilog and Verilog.
  • Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
  • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
  • Deep expertise in one or more of the following areas:
    • RTL Design and Microarchitecture
    • Functional Verification (UVM, SVA, Cocotb, testbench development)
    • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
    • Formal Verification and Coverage Closure
    • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
    • Analog/Mixed-Signal Design Verification
    • Hardware Specification Development and Technical Documentation
  • Ability to commit 20-40 hours per week with reliable weekday availability.
  • Strong written communication skills and the ability to work independently in a remote environment.
Preferred Qualifications
  • Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
  • Graduate research or industry experience in semiconductor design, verification, or computer architecture.
  • Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
  • Experience mentoring engineers or reviewing complex technical designs.
Why Join
  • Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
  • Apply your practical chip design and verification expertise to improve the next generation of AI models.
  • Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
  • Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.
Equal Opportunity
We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.
Contract & Engagement Details
  • Independent contractor engagement.
  • Fully remote with flexible working hours.
  • Expected commitment of approximately 20-40 hours per week.
  • Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
  • Work does not require access to confidential or proprietary information from any current or former employer.
  • Payments are issued weekly based on approved work completed.
  • At this time, we are unable to support H1-B or STEM OPT candidates.

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