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Packaging Director Semiconductor Jobs (NOW HIRING)

Thermo Fisher Scientific

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$123K - $180K/yr

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Packaging Director Semiconductor information

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$23.5K

$121.5K

$189.5K

How much do packaging director semiconductor jobs pay per year?

As of Jul 22, 2026, the average yearly pay for packaging director semiconductor in the United States is $121,522.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $147,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Packaging Director in the semiconductor industry, and why are they important?

To excel as a Packaging Director in semiconductors, you need deep expertise in semiconductor packaging technologies, materials science, and process optimization, often backed by an engineering degree and significant industry experience. Familiarity with industry-standard design software (like Cadence or Mentor Graphics), statistical process control tools, and relevant certifications such as Six Sigma is highly beneficial. Strong leadership, project management, and cross-functional communication skills set top candidates apart in this role. These capabilities are critical for driving innovation, ensuring product quality, and leading teams to meet the fast-paced demands of the semiconductor market.

What does a Packaging Director in the semiconductor industry do?

A Packaging Director in the semiconductor industry oversees the development and implementation of advanced packaging solutions for semiconductor devices. They manage teams responsible for designing, testing, and optimizing the processes that encase semiconductor chips to protect them, enhance performance, and enable integration into electronic products. Their role involves collaborating with engineering, manufacturing, and supply chain teams to ensure packaging innovations meet technical, cost, and quality requirements. Additionally, they stay updated on industry trends to maintain competitiveness and drive the adoption of new technologies. Effective leadership and strategic planning are key aspects of this position.

What is the difference between Packaging Director Semiconductor vs Packaging Engineer Semiconductor?

AspectPackaging Director SemiconductorPackaging Engineer Semiconductor
ResponsibilitiesOversees entire packaging operations, strategic planning, team leadershipDesigns, develops, and tests packaging solutions, executes project tasks
Required CredentialsBachelor's/Master's in Engineering, extensive industry experienceBachelor's in Engineering, relevant certifications often preferred
Work EnvironmentManagement level, strategic focus, cross-department collaborationTechnical role, hands-on design and testing, project-focused
Industry UsageCommonly used in large semiconductor companies and fabsUsed across R&D labs, manufacturing, and design firms

The Packaging Director Semiconductor focuses on strategic leadership and managing packaging operations, while the Packaging Engineer Semiconductor is more involved in technical design and development tasks. Both roles require engineering background, but differ in scope and seniority within the industry.

What are the main challenges faced by a Packaging Director in the semiconductor industry?

A Packaging Director in the semiconductor industry often navigates challenges such as managing rapid advancements in packaging technologies, ensuring cost-effective production while maintaining high quality standards, and coordinating cross-functional teams across engineering, manufacturing, and supply chain. Staying ahead of competitors requires continuous learning and adaptation, as well as fostering strong partnerships with vendors and internal R&D teams. Additionally, balancing tight project timelines with the need for innovation and reliability in product design is a key aspect of this role.
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What cities are hiring for Packaging Director Semiconductor jobs? Cities with the most Packaging Director Semiconductor job openings:
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Packaging Director Semiconductor jobs near you
Infographic showing various Packaging Director Semiconductor job openings in the United States as of July 2026, with employment types broken down into 1% As Needed, 84% Full Time, 12% Part Time, 1% Temporary, and 2% Contract. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution, with an average salary of $121,522 per year, or $58.4 per hour.

Director Semiconductor Technologies

JRC Careers

Sunnyvale, CA • On-site

Full-time

Posted 22 days ago

Job description

Who We Are (video)
At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission-critical microelectronics solutions, aerospace systems engineering, and cutting-edge research and development. By joining JRC, you'll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.
Join JRC's Semiconductor Technology Team!
We are seeking a technically commanding Senior Manager of Semiconductor Technologies to manage our core development efforts in radiation-hardened microelectronics. Reporting directly to the Vice President of Semiconductor Technologies, this role oversees the strategic direction and technical execution of our next-generation LEAP Standard Cell Library and leads the development of proprietary simulation software for predicting reliability and radiation-induced error rates.
What You'll Do
  • Mentor, manage, and grow a high-performing multidisciplinary team of device physicists, circuit designers, and software engineers.
  • Serve as the subject matter expert on Semiconductor Device Physics for radiation effects, including TID, SEE, and SEU.
  • Define the technical strategy and roadmap for Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
  • Interface regularly with government and DoW customers, DIB customers and strategic partners, and attend relevant conferences. Contribute to BD pipeline assessments and capture tracking. Provide hands-on assistance with technical content of capture proposals and work seamlessly with the contracts and proposal execution teams.
  • Direct the development and enhancement of proprietary software tools used for analyzing circuit reliability and radiation-induced error rates.
  • Oversee advanced library characterization and simulations to optimize Power, Performance, and Area (PPA) in harsh environments.
  • Manage relationships with external foundry partners to influence Multi-Product Wafer (MPW) execution and interface directly with customers to ensure technical quality control.

What You Bring
  • Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience, OR a Master's degree with 6+ years of direct industry experience, OR a Bachelor's degree with 8+ years of experience.
  • Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
  • Deep foundational knowledge of semiconductor device physics and semiconductor design methodologies and principles.
  • Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
  • Demonstrated experience being involved in test-chip designs and MPW execution.
  • Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
  • Extensive experience with semiconductor device & design simulation tools, specifically for library characterization.
  • Demonstrated track record of managing or leading engineers for a minimum of 5 years.
  • Demonstrated end-to-end track record of steering execution of complex technical projects from initial concept/feasibility phase through completion.
  • Outstanding communication and presentation skills

☆Bonus Points
  • Ph.D. with 5+ years, Master's with 9+ years, or Bachelor's with 10+ years of direct industry experience.
  • Proven leadership running and scaling high-performing multidisciplinary engineering teams while owning technical strategy and roadmaps.
  • Demonstrated success shaping government-focused proposals/contracts and contributing to BD pipelines and strategic captures.
  • Direct RHBD experience mitigating SEU/SEE, plus proficiency in C++, Python, and TCL for advanced simulation and automation.
  • Hands-on work with advanced FinFET and GAA nodes (e.g., Intel 18A) and a strong ability to rapidly learn new physics and technology platforms.

At JRC we offer...
  • A competitive compensation package
  • An exceptional employee benefits program, providing support for our team members' well-being and success
  • The chance to contribute to a high-profile Department of Defense programs and make a positive impact
  • A collaborative work environment where teamwork, creativity, and innovation thrive
  • Opportunities for professional growth and development, helping you advance your career

Apply