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Memory Layout Jobs (NOW HIRING)

STR

Software Reverse Engineer

Woburn, MA

$112K - $154K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

STR

Senior Reverse Engineer

Arlington, VA · On-site

$134K - $184K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

STR

Senior Reverse Engineer

Woburn, MA

$134K - $184K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

STR

Senior Reverse Engineer

Melbourne, FL

$134K - $184K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

STR

Software Reverse Engineer

Melbourne, FL · On-site

$112K - $154K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

Unity

Senior Software Engineer, 3D Systems & AI

Bellevue, WA · On-site

$137K - $181K/yr

... memory layout, allocation patterns, branch behavior, profiling, and performance tradeoffs in real-time systems. • Hands-on experience across multiple engine domains -- such as physics, animation ...

Micron Technology

PCB Layout Designer

Boise, ID · On-site

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... PCB Layout Designer Our vision is to transform how the world uses information to enrich life for ...

STR

Senior Reverse Engineer

Arlington, VA · On-site

$120K - $165K/yr

C/C++, Python, etc. • Proficiency in one or more Assembly Languages: x86, ARM, etc. • General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Preferred ...

STR

Software Reverse Engineer

Arlington, VA

$112K - $154K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

Micron

PCB Layout Designer

Boise, ID

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... PCB Layout Designer Our vision is to transform how the world uses information to enrich life for ...

Micron

Layout/Mask Designer

Boise, ID

Contribute to the development of new memory products by assisting with the overall layout and optimization of memory circuits. Build layout skillsets and techniques through on-the-job training and ...

Micron Technology

Layout/Mask Designer

Boise, ID · On-site

Contribute to the development of new memory products by assisting with the overall layout and optimization of memory circuits. Build layout skillsets and techniques through on-the-job training and ...

STR

Senior Reverse Engineer

Arlington, VA · On-site

$120K - $165K/yr

C/C++, Python, etc. • Proficiency in one or more Assembly Languages: x86, ARM, etc. • General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Preferred ...

Micron Technology

Layout Engineer, DEG

Boise, ID · On-site

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our layout engineering team drives the physical design foundations behind Micron's industry-leading ...

STR

Senior Reverse Engineer

San Diego, CA

$134K - $184K/yr

General understanding of reverse engineering fundamentals: memory layout, calling conventions, etc. Nice to haves: * Vulnerability research and analysis * Knowledge of weaponizing discovered ...

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Memory Layout information

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$11

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$67

How much do memory layout jobs pay per hour?

As of Jun 29, 2026, the average hourly pay for memory layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Memory Layout position, and why are they important?

To excel in a Memory Layout role, you need a strong background in digital design, computer architecture, and semiconductor device physics, typically supported by a degree in electrical engineering or a related field. Experience with specialized EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics, along with knowledge of relevant process design kits (PDKs), is essential. Strong attention to detail, time management, and the ability to communicate effectively with cross-functional teams are valuable soft skills. These capabilities ensure optimal memory circuit performance, reliability, and seamless collaboration in fast-paced semiconductor development environments.

What is a Memory Layout job?

A Memory Layout job involves designing and optimizing the physical arrangement of memory structures in integrated circuits (ICs) to ensure efficient performance, minimal power consumption, and optimal area utilization. Professionals in this field work closely with circuit designers and verification engineers to implement memory blocks such as SRAM, DRAM, and register files. They use Electronic Design Automation (EDA) tools to create layouts that meet design specifications while adhering to manufacturing constraints and design rules.

What are typical daily responsibilities for someone working in Memory Layout within a semiconductor company?

As a Memory Layout professional, your day-to-day tasks will include translating memory circuit schematics into physical layouts, optimizing layouts for performance and manufacturability, and running verification checks such as DRC (Design Rule Check) and LVS (Layout Versus Schematic). You will frequently collaborate with circuit designers, process engineers, and verification teams to ensure the layout meets both functional and manufacturing requirements. The role may also involve creating layout documentation and responding to feedback from fabrication teams. This position is detail-oriented and requires a blend of technical expertise and teamwork to ensure robust, efficient memory products. Over time, a strong performance in this role can open doors to lead layout, architecture, or design management positions.

More about Memory Layout jobs
What states have the most Memory Layout jobs? States with the most job openings for Memory Layout jobs include:
What job categories do people searching Memory Layout jobs look for? The top searched job categories for Memory Layout jobs are:
Memory Layout jobs near you
Infographic showing various Memory Layout job openings in the United States as of June 2026, with employment types broken down into 82% Full Time, and 18% Part Time. Highlights an 100% In-person job distribution, with an average salary of $45,402 per year, or $21.8 per hour.
Senior Staff Machine Learning Software Engineer

Senior Staff Machine Learning Software Engineer

Foresite Labs

San Diego, CA • On-site

$202K - $215K/yr

Full-time

Posted 7 days ago

Key responsibilities

  • Turn research prototypes into production inference components with explicit latency, throughput, memory, and accuracy budgets.

  • Optimize the execution path of inference components, including tensor layout, host/device transfers, batching strategy, kernel launch overhead, mixed precision, quantization, and memory reuse.

  • Build and maintain inference-adjacent evaluation machinery such as calibration checks, confidence behavior, regression detection, dataset slices, and failure-mode reporting tied to product metrics.

Job description

Senior Staff Machine Learning Software Engineer
Location: San Diego, CA
Job Type: Full-Time
Salary Range: $202K - 215K
Sr. Staff ML/Software Engineer
We are building a product where learned models and compute-heavy inference components have to run inside a tight local runtime budget. Research code is only the starting point. This role owns the path from a working prototype to production inference that is measured, packaged, tested, and ready for repeated use in the field.
You will work closely with the people developing the underlying algorithms, but your ownership is different: production readiness, performance, reliability, and the engineering boundary between exploratory model work and shipped execution. The strongest fit is someone who can explain the bottleneck they found, the number they moved, the tradeoff they accepted, and the test that kept the fix from regressing.
If your best work is making inference faster, smaller, more predictable, and easier to ship, this role is likely a good match.
What You'll Own
  • Turning research prototypes into production inference components with explicit latency, throughput, memory, and accuracy budgets
  • Optimizing the execution path: tensor layout, host/device transfers, batching strategy, kernel launch overhead, mixed precision, quantization, and memory reuse
  • Writing or tuning Rust, C++, and CUDA where framework-level optimization is not enough, then validating the improvement with profiler output and release-facing tests
  • Building inference-adjacent evaluation machinery: calibration checks, confidence behavior, regression detection, dataset slices, and failure-mode reporting tied to product metrics
  • Maintaining the deployment contract: model artifacts, runtime integration, versioning, reproducibility, and performance gates that block unsafe changes

• Algorithm research and novel model design live on a separate track. You will collaborate with that team, translate prototypes into production constraints, and surface shipping risks early when a design needs to change.
Education and Experience
A PhD (6+ years), MS (10+ years) or BS/BA (12+ years) of experience in life sciences or technology.
Must have demonstrated leadership or ownership with 2 of the 5 areas referenced below successfully:
Shipped constrained inference. You have personally moved a model or learned component from prototype to deployed runtime with a real latency, throughput, memory, or power budget. You can name the target, the bottleneck, and the change that closed the gap.
Rust/C++ at shipping depth. You have written production code in Rust or modern C++ where correctness, latency, memory layout, and ownership boundaries mattered. You can reason about the runtime behavior of the code you ship, not just its API surface.
CUDA and accelerator-aware execution. You are comfortable below Python: custom CUDA extensions or kernels, host/device memory movement, launch overhead, profiler traces, and the practical tradeoffs between framework convenience and a purpose-built implementation.
Performance-native judgment. You reason in wall-clock time, memory movement, launch overhead, bandwidth, numerical precision, and error budgets without needing those constraints added late in review.
Production engineering discipline. You define typed interfaces, deterministic behavior, reproducible artifacts, meaningful tests, and clean handoffs with upstream research code.
Strongly Preferred
  • Rust at shipping depth, especially FFI boundaries, pyo3 / maturin, async runtimes, or performance-sensitive service code
  • Inference on constrained local hardware, embedded systems, edge devices, or budget-bound accelerator deployments
  • Quantization, mixed precision, model compression, or kernel fusion that shipped beyond a benchmark notebook
  • Calibration or confidence estimation used on production outputs, with monitoring or regression checks attached
  • Public or shareable evidence of engineering quality: code, technical writing, postmortems, talks, or a concrete shipped system you can discuss
  • Comfort using AI-assisted development tools while still owning correctness, tests, and review quality

Nice to Have
  • Real-time or near-real-time signal-processing systems
  • Products that combine learned models with deterministic numerical code
  • Rust- or C++-based inference or numerical pipelines, including custom FFI to CUDA, cuDNN, TensorRT, or similar accelerator libraries

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