Overview of Role In the role of Senior Memory Layout Engineer, you will primarily be responsible for challenging and cutting-edge custom layout design and be involved in R&D projects implemented on ...
Overview of Role In the role of Senior Memory Layout Engineer, you will primarily be responsible for challenging and cutting-edge custom layout design and be involved in R&D projects implemented on ...
Staff Firmware Engineer
Toronto, ON · Hybrid
CA$100K - CA$500K/yr
You have 5+ years of experience in embedded firmware or low-level system software development, with strong C/C++ fundamentals across memory layout, interrupts, concurrency, and bare-metal or RTOS ...
Staff Firmware Engineer
Toronto, ON · Hybrid
CA$100K - CA$500K/yr
You have 5+ years of experience in embedded firmware or low-level system software development, with strong C/C++ fundamentals across memory layout, interrupts, concurrency, and bare-metal or RTOS ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Develop, optimize, and benchmark GPU kernels (hand-tuned and compiler-generated) using techniques such as fusion, autotuning, and memory/layout optimization; build and extend high-level DSLs and ...
Develop, optimize, and benchmark GPU kernels (hand-tuned and compiler-generated) using techniques such as fusion, autotuning, and memory/layout optimization; build and extend high-level DSLs and ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. * Publish and ...
Director of IP Development
Kitchener, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Quick apply
Director of IP Development
Kitchener, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Hardware Designer
Ottawa, ON · On-site
CA$95K - CA$145K/yr
You'll collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout ... and memory busses * Conduct design simulations using LTSpice and prove circuits using prototype ...
Quick apply
Hardware Designer
Ottawa, ON · On-site
CA$95K - CA$145K/yr
You'll collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout ... and memory busses * Conduct design simulations using LTSpice and prove circuits using prototype ...
Director of IP Development
Toronto, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Quick apply
Director of IP Development
Toronto, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Director of IP Development
Toronto, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Quick apply
Director of IP Development
Toronto, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Director of IP Development
Kitchener, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Quick apply
Director of IP Development
Kitchener, ON · Hybrid
$180K - $200K/yr
Overseeing or directly engaging in the physical layout implementation process, upholding crucial ... A strong grasp of interconnect and memory interfaces, inclusive of PCIE and LPDDR. * Highly ...
Hardware Designer
Kitchener, ON · On-site
CA$95K - CA$145K/yr
You'll collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout ... and memory busses * Conduct design simulations using LTSpice and prove circuits using prototype ...
Quick apply
Hardware Designer
Kitchener, ON · On-site
CA$95K - CA$145K/yr
You'll collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout ... and memory busses * Conduct design simulations using LTSpice and prove circuits using prototype ...
Strong sense of design, layout, and interaction * Comfortable working hybrid from our Kanata office ... Familiarity with embedded constraints (performance, memory) * Experience with embedded software ...
Strong sense of design, layout, and interaction * Comfortable working hybrid from our Kanata office ... Familiarity with embedded constraints (performance, memory) * Experience with embedded software ...
Senior Electrical Engineer & Team Lead
Toronto, ON · On-site
CA$133K - CA$183K/yr
Experience with schematic and layout of processors, FPGAs, SoCs, DAC/ADCs or other high speed digital components * Familiar with various memory including QSPI, UFS, DDR3/4, eMMC * Experience with ...
Senior Electrical Engineer & Team Lead
Toronto, ON · On-site
CA$133K - CA$183K/yr
Experience with schematic and layout of processors, FPGAs, SoCs, DAC/ADCs or other high speed digital components * Familiar with various memory including QSPI, UFS, DDR3/4, eMMC * Experience with ...
Electrical Design Engineer
Toronto, ON · On-site
CA$113K - CA$163K/yr
... layout oversight, integration, verification, and design validation testing. * Proven experience ... Experience designing memory subsystems utilizing technologies such as QSPI, eMMC, DDR3/DDR4, UFS ...
Electrical Design Engineer
Toronto, ON · On-site
CA$113K - CA$163K/yr
... layout oversight, integration, verification, and design validation testing. * Proven experience ... Experience designing memory subsystems utilizing technologies such as QSPI, eMMC, DDR3/DDR4, UFS ...
Hardware Designer (Future Opportunities)
CA$90K - CA$140K/yr
Collaborate closely with the PCB layout team to produce high-quality, reliable boards that meet ... Proficiency with microcontrollers, memory interfaces, and embedded hardware architecture.
Hardware Designer (Future Opportunities)
CA$90K - CA$140K/yr
Collaborate closely with the PCB layout team to produce high-quality, reliable boards that meet ... Proficiency with microcontrollers, memory interfaces, and embedded hardware architecture.
Circuit Analyst
Nepean, ON · On-site
... memory and/or System on a Chip devices to reveal the innovation that others cannot. As a skilled ... Preparing die floor plan analysis, standard cell schematic and layout extraction as well as ...
Quick apply
Circuit Analyst
Nepean, ON · On-site
... memory and/or System on a Chip devices to reveal the innovation that others cannot. As a skilled ... Preparing die floor plan analysis, standard cell schematic and layout extraction as well as ...
... layout tools and workflows. * Work with the tech art and engineering teams to help establish performance and memory budgets to set achievable targets for world density. Qualifications: * 5+ Years ...
... layout tools and workflows. * Work with the tech art and engineering teams to help establish performance and memory budgets to set achievable targets for world density. Qualifications: * 5+ Years ...
... way through layout, packaging, prototype validation and production ramp up. What You Can Expect . * Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network ...
... way through layout, packaging, prototype validation and production ramp up. What You Can Expect . * Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network ...
... layout, packaging, prototype validation and production ramp up. What You Can Expect * Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute ...
... layout, packaging, prototype validation and production ramp up. What You Can Expect * Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute ...
Memory Layout information
See Ontario salary details
$10.34 - $15.63
18% of jobs
$16.85 is the 25th percentile. Wages below this are outliers.
$15.63 - $20.91
30% of jobs
The median wage is $21.62 / hr.
$20.91 - $26.20
16% of jobs
$26.20 - $31.49
11% of jobs
$31.78 is the 75th percentile. Wages above this are outliers.
$31.49 - $36.78
10% of jobs
$36.78 - $42.07
5% of jobs
$42.07 - $47.36
3% of jobs
$47.36 - $52.64
2% of jobs
$52.64 - $57.93
2% of jobs
$57.93 - $63.22
1% of jobs
$63.22 - $68.51
2% of jobs
$10
$28
$68
How much do memory layout jobs pay per hour?
What are the key skills and qualifications needed to thrive in the Memory Layout position, and why are they important?
To excel in a Memory Layout role, you need a strong background in digital design, computer architecture, and semiconductor device physics, typically supported by a degree in electrical engineering or a related field. Experience with specialized EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics, along with knowledge of relevant process design kits (PDKs), is essential. Strong attention to detail, time management, and the ability to communicate effectively with cross-functional teams are valuable soft skills. These capabilities ensure optimal memory circuit performance, reliability, and seamless collaboration in fast-paced semiconductor development environments.
What is a Memory Layout job?
A Memory Layout job involves designing and optimizing the physical arrangement of memory structures in integrated circuits (ICs) to ensure efficient performance, minimal power consumption, and optimal area utilization. Professionals in this field work closely with circuit designers and verification engineers to implement memory blocks such as SRAM, DRAM, and register files. They use Electronic Design Automation (EDA) tools to create layouts that meet design specifications while adhering to manufacturing constraints and design rules.
What are typical daily responsibilities for someone working in Memory Layout within a semiconductor company?
As a Memory Layout professional, your day-to-day tasks will include translating memory circuit schematics into physical layouts, optimizing layouts for performance and manufacturability, and running verification checks such as DRC (Design Rule Check) and LVS (Layout Versus Schematic). You will frequently collaborate with circuit designers, process engineers, and verification teams to ensure the layout meets both functional and manufacturing requirements. The role may also involve creating layout documentation and responding to feedback from fabrication teams. This position is detail-oriented and requires a blend of technical expertise and teamwork to ensure robust, efficient memory products. Over time, a strong performance in this role can open doors to lead layout, architecture, or design management positions.
Other
Posted 24 days ago
TSMC rating
8.2
Based on 19 frontline employees who took The Breakroom Quiz
37th of 139 rated electronics manufacturers
Job description
Company Introduction: TSMC Design Technology Canada Inc. (OTTAWA) (TDTC)
Immerse yourself in cutting-edge circuit R&D at TSMC Design Technology Canada, Inc. (TDTC), a proud part of Taiwan Semiconductor Manufacturing Company Limited (TSMC)-a pioneer in the semiconductor foundry industry since 1987. Located in Kanata, Ottawa's thriving high-tech region, TDTC has been driving advancements in semiconductor process technologies since its inception in 2007. Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and layout. We invite passionate innovators to join us in our pursuit of excellence and help redefine the boundaries of technology development in Ottawa, Ontario, Canada.
Overview of Role
In the role of Senior Memory Layout Engineer, you will primarily be responsible for challenging and cutting-edge custom layout design and be involved in R&D projects implemented on the world's most advanced CMOS/FinFET processes (5nm and below). This will involve detailed implementation of the high speed and high-density memory compilers and high-speed analog circuits. The successful candidate must demonstrate a high level of ability to estimate, plan and coordinate layout work.
You will perform advanced custom layout implementing IC design in deep-submicron CMOS/FinFET. In addition, you will accomplish compact high performance memory layout: Memory Array, Periphery and Tiler Coding, etc. using industry standard custom CAD tools, layout, DRC, LVS, RC Extraction etc.
Qualifications:
- Bachelor's or master's degree in Computer Science, Computer Engineering, Physics, Mathematics, or a related discipline
- 8+ years of experience in advanced Semiconductor Memory Layout design
- Advanced FinFET nodes, TSMC 16 nanometer and below
- OTP or other types of memory layout design.
- Layout techniques to meet ESD, latch up, antenna requirements
- Verification tools: ICV, Calibre
- Design tool(s): Custom Compiler, Cadence Virtuoso or equivalent
- Scripting language: TCL, etc.
- Talent in advanced layout design, verification, and documentation of memory circuits
- Hands-on working knowledge of CAD tools; expert user of at least one large CAD custom layout tool flow
- Demonstrated knowledge writing scripts (Cadence Skill, Pearl, Compiler-Tiler, Linux
Required Competencies:
- Ability to deliver expert/ high quality layouts creatively and independently
- Exceptional time management skills and work habits, with experience working under pressure to deliver
- Proven ability to learn and adapt to new processes and design styles or constraints
- A seasoned team player with enhanced communication skills; excellent working knowledge of English (written and oral) is mandatory
- Ability to work well with teams in diverse locations (e.g., USA, Taiwan)
- Advanced ability to analyze and problem-solve
- Well established listening, understanding, and responding skills, and ability to appreciate and interact with cross-functional teams
- Highly developed attention to detail and multi-tasking skills
- Demonstrated team leadership is a strong asset
TSMC Core Values
At TSMC, we invite talented individuals who share our vision and values to contribute to our continued success. Our core values are the foundation of our culture, guiding every decision and action. We seek applicants who deeply resonate with these principles and embody them in their work:
- Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.
- Commitment: Employees are dedicated to the company, view the company's success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees.
- Innovation: Innovation is the wellspring of the Company's growth. It means more than new ideas; it means putting ideas into practice.
- Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term.
(For more details on TSMC's Core Values, please visithttps://www.tsmc.com/english/aboutTSMC/values)
Diversity statement
TSMC Design Technology Canada Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunities for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, genetic information, or any other characteristic protected by the Employment Equity Act and other application legislation in Canada.
TSMC is an equal opportunity employer embracing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_ACCOMMODATIONS@TSMC.COM. TSMC confirms to all applicants its commitment to meet TSMC's obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.