SRAM Mask Layout Designer
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean ... Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$134K - $245K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
Costa Mesa, CA · On-site
$129K - $171K/yr
... memory layout, cache behavior, and contention as entity counts grow • Custom Entity-Component-System architecture that underpins the entire simulator: entity lifecycle, component storage, system ...
Costa Mesa, CA · On-site
$129K - $171K/yr
... memory layout, cache behavior, and contention as entity counts grow • Custom Entity-Component-System architecture that underpins the entire simulator: entity lifecycle, component storage, system ...
Burlington, VT · On-site
$104K - $140K/yr
Play a leading role in developing full-custom SRAM memory layout and sign-off verification flows * Collaborate with circuit designers to translate schematics into efficient, high-performance layouts ...
Burlington, VT · On-site
$104K - $140K/yr
Play a leading role in developing full-custom SRAM memory layout and sign-off verification flows * Collaborate with circuit designers to translate schematics into efficient, high-performance layouts ...
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
$62.25 - $122/hr
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
$62.25 - $122/hr
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
Play a leading role in developing full-custom SRAM memory layout and sign-off verification flows * Collaborate with circuit designers to translate schematics into efficient, high-performance layouts ...
Play a leading role in developing full-custom SRAM memory layout and sign-off verification flows * Collaborate with circuit designers to translate schematics into efficient, high-performance layouts ...
Richardson, TX · On-site
$62.25 - $122/hr
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
Richardson, TX · On-site
$62.25 - $122/hr
As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to ...
... memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team. The chosen candidate should have a minimum of 5-10 years of memory ...
... memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team. The chosen candidate should have a minimum of 5-10 years of memory ...
$131K - $173K/yr
Ability to reason about performance-sensitive code - cache behavior, memory layout, algorithmic complexity * Clear technical communication and ability to work in a large, shared codebase and ...
$131K - $173K/yr
Ability to reason about performance-sensitive code - cache behavior, memory layout, algorithmic complexity * Clear technical communication and ability to work in a large, shared codebase and ...
San Francisco, CA · On-site
$123K - $169K/yr
Own the optimization pipeline for the models you ship: model export, graph transformation, operator fusion, memory-layout planning, and hardware-specific tuning across NPU, mobile GPU, and desktop ...
San Francisco, CA · On-site
$123K - $169K/yr
Own the optimization pipeline for the models you ship: model export, graph transformation, operator fusion, memory-layout planning, and hardware-specific tuning across NPU, mobile GPU, and desktop ...
$15.74 is the 25th percentile. Wages below this are outliers.
$11.06 - $16.22
28% of jobs
The median wage is $18.92 / hr.
$16.22 - $21.37
43% of jobs
$22.38 is the 75th percentile. Wages above this are outliers.
$21.37 - $26.53
23% of jobs
$26.53 - $31.69
6% of jobs
$31.69 - $36.84
0% of jobs
$36.84 - $42
0% of jobs
$42 - $47.16
0% of jobs
$47.16 - $52.32
0% of jobs
$52.32 - $57.47
0% of jobs
$57.47 - $62.63
0% of jobs
$62.63 - $67.79
0% of jobs
$11
$21
$67
To excel in a Memory Layout role, you need a strong background in digital design, computer architecture, and semiconductor device physics, typically supported by a degree in electrical engineering or a related field. Experience with specialized EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics, along with knowledge of relevant process design kits (PDKs), is essential. Strong attention to detail, time management, and the ability to communicate effectively with cross-functional teams are valuable soft skills. These capabilities ensure optimal memory circuit performance, reliability, and seamless collaboration in fast-paced semiconductor development environments.
A Memory Layout job involves designing and optimizing the physical arrangement of memory structures in integrated circuits (ICs) to ensure efficient performance, minimal power consumption, and optimal area utilization. Professionals in this field work closely with circuit designers and verification engineers to implement memory blocks such as SRAM, DRAM, and register files. They use Electronic Design Automation (EDA) tools to create layouts that meet design specifications while adhering to manufacturing constraints and design rules.
As a Memory Layout professional, your day-to-day tasks will include translating memory circuit schematics into physical layouts, optimizing layouts for performance and manufacturability, and running verification checks such as DRC (Design Rule Check) and LVS (Layout Versus Schematic). You will frequently collaborate with circuit designers, process engineers, and verification teams to ensure the layout meets both functional and manufacturing requirements. The role may also involve creating layout documentation and responding to feedback from fabrication teams. This position is detail-oriented and requires a blend of technical expertise and teamwork to ensure robust, efficient memory products. Over time, a strong performance in this role can open doors to lead layout, architecture, or design management positions.

Design layout for custom memories and other digital circuits based on provided schematics.
Own the entire layout process from initial floorplanning to memory construction to physical verification.
Use industry standard verification tools to validate LVS, DRC, ERC and perform layout fixes as needed.
9.6
Based on 5 frontline employees who took The Breakroom Quiz
6th of 192 rated software companies
Sourced by ZipRecruiter
Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.
Technology, communication and media
10,000+ Employees
San Diego, CA, US
1985