SRAM Mask Layout Designer
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
Austin, TX · On-site
Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.
San Diego, CA · On-site
$164K - $246K/yr
Layout planning and supervision * Interacting with CAD team for full verification and model generation * Interacting with SoC teams (CPU, GPU, Modem, etc) to define memory PPA targets. Qualifications ...
San Diego, CA · On-site
$164K - $246K/yr
Layout planning and supervision * Interacting with CAD team for full verification and model generation * Interacting with SoC teams (CPU, GPU, Modem, etc) to define memory PPA targets. Qualifications ...
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
Austin, TX · On-site
Experience designing low noise, low power datapaths or Memory layout structures, etc.
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$166K - $296K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
$137K - $250K/yr
Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...
Richardson, TX · On-site
$85.41 - $168.07/hr
... memory solutions purpose-built for emerging AI systems and applications.As a **Principal Layout Designer in the Next-generation HBM Architecture Team**, you will drive layout for 3D-stacked, high ...
Richardson, TX · On-site
$85.41 - $168.07/hr
... memory solutions purpose-built for emerging AI systems and applications.As a **Principal Layout Designer in the Next-generation HBM Architecture Team**, you will drive layout for 3D-stacked, high ...
Santa Clara, CA · On-site
$144.60 - $263.80/hr
Experience in memory compiler development is considered a plus, but not required. * Experience designing low noise, low power datapaths or memory layout structures, etc. At Apple, base pay is one ...
Santa Clara, CA · On-site
$144.60 - $263.80/hr
Experience in memory compiler development is considered a plus, but not required. * Experience designing low noise, low power datapaths or memory layout structures, etc. At Apple, base pay is one ...
Costa Mesa, CA · On-site
$129K - $171K/yr
... memory layout, cache behavior, and contention as entity counts grow • Custom Entity-Component-System architecture that underpins the entire simulator: entity lifecycle, component storage, system ...
Costa Mesa, CA · On-site
$129K - $171K/yr
... memory layout, cache behavior, and contention as entity counts grow • Custom Entity-Component-System architecture that underpins the entire simulator: entity lifecycle, component storage, system ...
... memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team. The chosen candidate should have a minimum of 5-10 years of memory ...
... memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team. The chosen candidate should have a minimum of 5-10 years of memory ...
$131K - $173K/yr
Ability to reason about performance-sensitive code - cache behavior, memory layout, algorithmic complexity * Clear technical communication and ability to work in a large, shared codebase and ...
$131K - $173K/yr
Ability to reason about performance-sensitive code - cache behavior, memory layout, algorithmic complexity * Clear technical communication and ability to work in a large, shared codebase and ...
San Jose, CA · On-site
$72 - $122/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...
San Jose, CA · On-site
$72 - $122/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...
San Jose, CA · On-site
$72 - $122/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...
San Jose, CA · On-site
$72 - $122/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...
Richardson, TX · On-site
$90 - $130/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Knowledge of layout synthesis and place and route techniques * Experience with LVS and DRC tools ...
New
Richardson, TX · On-site
$90 - $130/hr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Knowledge of layout synthesis and place and route techniques * Experience with LVS and DRC tools ...
New
$15.74 is the 25th percentile. Wages below this are outliers.
$11.06 - $16.22
28% of jobs
The median wage is $18.92 / hr.
$16.22 - $21.37
43% of jobs
$22.38 is the 75th percentile. Wages above this are outliers.
$21.37 - $26.53
23% of jobs
$26.53 - $31.69
6% of jobs
$31.69 - $36.84
0% of jobs
$36.84 - $42
0% of jobs
$42 - $47.16
0% of jobs
$47.16 - $52.32
0% of jobs
$52.32 - $57.47
0% of jobs
$57.47 - $62.63
0% of jobs
$62.63 - $67.79
0% of jobs
$11
$21
$67
A Memory Layout job involves designing and optimizing the physical arrangement of memory structures in integrated circuits (ICs) to ensure efficient performance, minimal power consumption, and optimal area utilization. Professionals in this field work closely with circuit designers and verification engineers to implement memory blocks such as SRAM, DRAM, and register files. They use Electronic Design Automation (EDA) tools to create layouts that meet design specifications while adhering to manufacturing constraints and design rules.
As a Memory Layout professional, your day-to-day tasks will include translating memory circuit schematics into physical layouts, optimizing layouts for performance and manufacturability, and running verification checks such as DRC (Design Rule Check) and LVS (Layout Versus Schematic). You will frequently collaborate with circuit designers, process engineers, and verification teams to ensure the layout meets both functional and manufacturing requirements. The role may also involve creating layout documentation and responding to feedback from fabrication teams. This position is detail-oriented and requires a blend of technical expertise and teamwork to ensure robust, efficient memory products. Over time, a strong performance in this role can open doors to lead layout, architecture, or design management positions.
To excel in a Memory Layout role, you need a strong background in digital design, computer architecture, and semiconductor device physics, typically supported by a degree in electrical engineering or a related field. Experience with specialized EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics, along with knowledge of relevant process design kits (PDKs), is essential. Strong attention to detail, time management, and the ability to communicate effectively with cross-functional teams are valuable soft skills. These capabilities ensure optimal memory circuit performance, reliability, and seamless collaboration in fast-paced semiconductor development environments.
States with the most job openings for Memory Layout jobs include:
The top searched job categories for Memory Layout jobs are:

8.8
Based on 11 frontline employees who took The Breakroom Quiz
48th of 245 rated software companies
Sourced by ZipRecruiter
Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.
Technology, communication and media
10,000+ Employees
San Diego, CA, US
1985