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Memory Layout Jobs (NOW HIRING)

Pacer Group

Memory Layout Engineer

Irvine, CA · On-site

Memory Layout Engineer Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ) Job Duration: 3 Months, Contract to Hire Job Responsibilities: * Design and implement custom memory ...

Qualcomm

SRAM Mask Layout Designer

Austin, TX · On-site

Work independently and execute memory layout with little supervision. * Provide realistic schedules for layout completion. * Provide insight into strategic decisions regarding memory layout and area.

Apple

Digital Layout Design Engineer

Austin, TX

$134K - $245K/yr

Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...

Apple

Digital Layout Design Engineer

Austin, TX

$134K - $245K/yr

Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...

Apple

Digital Layout Design Engineer

Austin, TX

$134K - $245K/yr

Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...

Apple

Digital Layout Design Engineer

Austin, TX · On-site

$134K - $245K/yr

Experience in memory compiler development is considered a plus, but not required. Experience designing low noise, low power datapaths or Memory layout structures, etc. Minimum Qualifications ...

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...

Micron

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ...

Coram AI

Robotics Software Engineer

Sunnyvale, CA · On-site

... memory layout, CPU utilization, and concurrency patterns • Debug complex production issues involving race conditions, memory fragmentation, and performance bottlenecks • Profile systems using low ...

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How much do memory layout jobs pay per hour?

As of Jun 7, 2026, the average hourly pay for memory layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Memory Layout position, and why are they important?

To excel in a Memory Layout role, you need a strong background in digital design, computer architecture, and semiconductor device physics, typically supported by a degree in electrical engineering or a related field. Experience with specialized EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics, along with knowledge of relevant process design kits (PDKs), is essential. Strong attention to detail, time management, and the ability to communicate effectively with cross-functional teams are valuable soft skills. These capabilities ensure optimal memory circuit performance, reliability, and seamless collaboration in fast-paced semiconductor development environments.

What is a Memory Layout job?

A Memory Layout job involves designing and optimizing the physical arrangement of memory structures in integrated circuits (ICs) to ensure efficient performance, minimal power consumption, and optimal area utilization. Professionals in this field work closely with circuit designers and verification engineers to implement memory blocks such as SRAM, DRAM, and register files. They use Electronic Design Automation (EDA) tools to create layouts that meet design specifications while adhering to manufacturing constraints and design rules.

What are typical daily responsibilities for someone working in Memory Layout within a semiconductor company?

As a Memory Layout professional, your day-to-day tasks will include translating memory circuit schematics into physical layouts, optimizing layouts for performance and manufacturability, and running verification checks such as DRC (Design Rule Check) and LVS (Layout Versus Schematic). You will frequently collaborate with circuit designers, process engineers, and verification teams to ensure the layout meets both functional and manufacturing requirements. The role may also involve creating layout documentation and responding to feedback from fabrication teams. This position is detail-oriented and requires a blend of technical expertise and teamwork to ensure robust, efficient memory products. Over time, a strong performance in this role can open doors to lead layout, architecture, or design management positions.

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Memory Layout jobs near you
Memory Layout Engineer

Memory Layout Engineer

Pacer Group

Irvine, CA • On-site

Contractor

Posted 24 days ago

Job description

Job Title: Memory Layout Engineer
Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ)
Job Duration: 3 Months, Contract to Hire
 
Job Responsibilities: 
  • Design and implement custom memory layouts for advanced technology nodes, collaborating with circuit designers to optimize performance, power, and area.
  • Mitigate layout design effects such as N-well proximity effect, diffusion spacing effect, and length of diffusion effects.
  • Collaborate with SoC partners to develop cutting-edge SRAM and Register File layout designs.
  • Participate in design reviews, to improve the quality of memory layouts.
  • Stay up to date with the latest industry trends and developments in memory layout design.
  • Perform physical verification (LVS, DRC, ANT, etc.) and debug memory layout.
  • Leading and mentoring junior layout engineers and providing guidance on layout techniques.
  • The ability to adhere to project timelines to ensure deliveries are met according to project schedules.
  • Effectively communicate with the design team to clarify and realize the layout requirements based on the schematic design intent.
  • Must be able to effectively switch between manufacturing nodes with minimal ramp.
Qualifications:
  •  7+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes including FinFET technologies
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Excellent programming skills in languages: SKILL, Perl; Python is a plus
  • Strong fundamentals in software development
  • Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
  • Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
  • Excellent communication and interpersonal skills
Mandatory Skills:
  • Synopsys/Cadence Analog Layout Tools (Preference: 5)
  • Memory design and layout (Preference: 5)
  • Python (Preference: 2)?