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Mask Design Engineer Jobs (NOW HIRING)

Superbeo

Analog Layout Design Engineer

Santa Clara, CA · On-site

Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...

Nvidia

Senior SRAM Layout Design Engineer

Austin, TX · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

Nvidia

Senior SRAM Layout Design Engineer

Durham, NC · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

Apple

PLL Design Engineer

Sunnyvale, CA

$129K - $225K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...

Apple

PLL Design Engineer

Sunnyvale, CA

$184K - $324K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...

QCi

PIC Engineering Reports to: Senior Director, PIC Engineering About Us Quantum Computing Inc. (QCi ... Drive process integration efforts including mask design, fabrication flow development, and ...

Apple

Wireless Design Engineer

San Diego, CA · On-site

As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system ...

Apple

Analog Circuit Design Engineer

Cupertino, CA · On-site

$249K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering Required. Preferred ...

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All JobsMask Design Engineer Jobs

Mask Design Engineer information

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$45K

$120.8K

$185.5K

How much do mask design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for mask design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What is a mask design engineer?

A mask design engineer is a professional who develops and designs photomasks used in semiconductor manufacturing to create integrated circuits. They use specialized software and collaborate with fabrication teams to ensure precise pattern transfer, often requiring knowledge of lithography processes and cleanroom environments.

What are some common challenges faced by Mask Design Engineers during the IC layout process?

Mask Design Engineers often encounter challenges such as adhering to strict design rules while maximizing layout efficiency and yield. They must manage complex design data, collaborate closely with circuit designers to implement feedback, and ensure that the mask layouts are optimized for both manufacturability and performance. Additionally, keeping up with evolving technology nodes and lithography constraints requires continuous learning and adaptation. Effective communication and attention to detail are crucial for overcoming these challenges and delivering high-quality mask designs on tight schedules.

What is the difference between Mask Design Engineer vs Photomask Fabrication Engineer?

AspectMask Design EngineerPhotomask Fabrication Engineer
Primary RoleDesigns photomasks used in semiconductor manufacturingManufactures and inspects photomasks based on design specifications
Skills & CertificationsKnowledge of CAD tools, semiconductor processes, optical designExperience with lithography, cleanroom protocols, quality control
Work EnvironmentDesign labs, CAD rooms, collaboration with chip designersCleanrooms, fabrication facilities, equipment operation
Industry UsageUsed in semiconductor and electronics manufacturingUsed in photomask production for chip fabrication

While both roles are essential in semiconductor manufacturing, the Mask Design Engineer focuses on creating the design files for photomasks, whereas the Photomask Fabrication Engineer handles the physical production and quality control of these masks. Both positions require specialized skills and work closely within the same industry but serve different stages of the mask creation process.

What are the key skills and qualifications needed to thrive as a Mask Design Engineer, and why are they important?

To thrive as a Mask Design Engineer, you need expertise in semiconductor device physics, layout design, and photolithography, typically supported by a degree in electrical engineering or a related field. Familiarity with CAD tools such as Cadence Virtuoso, Calibre, and other EDA software, as well as knowledge of industry standards like DRC/LVS checks, is essential. Attention to detail, problem-solving skills, and effective communication help ensure accuracy and collaboration within engineering teams. These skills and qualifications are critical for producing precise mask layouts that enable successful chip fabrication and yield.

What are Mask Design Engineers?

Mask Design Engineers are specialized professionals who create photomasks used in the fabrication of semiconductor devices. They use advanced computer-aided design (CAD) tools to translate circuit layouts into precise patterns that guide the manufacturing of microchips. These engineers work closely with circuit designers and fabrication teams to ensure accuracy and efficiency in chip production. Their expertise is crucial for achieving the high levels of miniaturization and performance required in modern electronics.

How much does a mask design engineer make at Nvidia?

A mask design engineer at Nvidia typically earns between $100,000 and $150,000 annually, depending on experience, location, and level. The role often requires expertise in semiconductor fabrication, mask layout, and CAD tools such as Calibre or Mentor Graphics.

What is the highest paid design job?

In design careers, roles such as industrial designers, user experience (UX) designers, and creative directors tend to have the highest salaries. Senior-level positions, especially those requiring advanced skills in software tools and leadership, typically offer the highest compensation in the design field.

What's a design engineer's salary?

A mask design engineer's salary typically ranges from $70,000 to $120,000 annually, depending on experience, location, and industry. Professionals with specialized skills in optical or mask design and proficiency in CAD tools tend to earn higher salaries.
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Mask Design Engineer jobs near you
Infographic showing various Mask Design Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.
Analog Layout Design Engineer

Analog Layout Design Engineer

Superbeo

Santa Clara, CA • On-site

Contractor

Posted 6 days ago

Job description

Job Title: Analog Layout Design Engineer
Job location: Santa Clara, CA, 95054
Job Duration: 3 Months, Contract to Hire
Job Description:
  • Experience with layout of cutting-edge high-performance, high-speed CMOS integrated circuits in older foundry CMOS process nodes in 40nm, 55nm, 65nm and 130nm following best practices from the industry.
  • Reviewing and analyzing floorplans and complex circuits with circuit designers
  • Running complete set of design verification tools available on AMS blocks
  • Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
  • Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
  • Be a great role model, by inspiring and motivating team, and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.
  • Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed
Qualifications:
  • 10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
  • Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.)
  • Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc.
  • High level of proficiency in custom, as well as standard cell-based, floorplanning and hierarchical layout assembly
  • Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems
  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports
  • Knowledge of CADENCE or MENTOR GRAPHICS layout tools.
  • Excellent interpersonal skills and able to work with remote teams
  • Synopsys/Cadence/Mentor Layout tools (Preference: 5)
  • Python (Preference: 3)
  • TSMC 7nm or 5nm (Preference: 3)
  • TSMC 3nm (Preference: 5)