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Layout Engineer Jobs in California (NOW HIRING)

Pacer Group

Memory Layout Engineer

Irvine, CA · On-site

Memory Layout Engineer Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ) Job Duration: 3 Months, Contract to Hire Job Responsibilities: * Design and implement custom memory ...

TetraMem Inc

Analog Layout Engineer

San Jose, CA · On-site

$110K - $300K/yr

The Analog Layout Engineer will be responsible for designing and implementing analog and mixed-signal layout designs for integrated circuits. This role requires a strong understanding of analog ...

Apple

Analog Layout Engineer

Cupertino, CA · On-site

$249.20K/yr

As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will ...

Apple

Analog Layout Engineer

Cupertino, CA · On-site

$163.30K - $290.10K/yr

The team is searching for a self-motivating engineer for the role of Analog Layout Engineer. As a member of the Analog Layout team, you will be working on the leading-edge technologies to build best ...

Apple

Analog Layout Engineer

Cupertino, CA

$172.10K - $305.60K/yr

As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will ...

Apple

Analog Layout Engineer

Cupertino, CA

$172.10K - $305.60K/yr

As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will ...

Apple

Analog Layout Engineer

Cupertino, CA · On-site

$163.30K - $290.10K/yr

The team is searching for a self-motivating engineer for the role of Analog Layout Engineer. As a member of the Analog Layout team, you will be working on the leading-edge technologies to build best ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Apple

RFIC Layout Engineer

Irvine, CA · On-site

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS ...

Apple

RFIC Layout Engineer

Irvine, CA · On-site

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

Apple

RFIC Layout Engineer

Irvine, CA

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

Apple

RFIC Layout Engineer

Irvine, CA

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

Analog Layout Engineer

Cupertino, CA · On-site

$115.71K - $203K/yr

The team is searching for a self-motivating engineer for the role of Analog Layout Engineer. As a member of the Analog Layout team, you will be working on the leading-edge technologies to build best ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237.20K/yr

Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration: Long Term Responsibilities: Senior layout designer, will be responsible for layout of high-performance analog ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

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All JobsLayout Engineer JobsLayout Engineer Jobs in California

Layout Engineer information

See California salary details

$44.4K

$119.3K

$183.1K

How much do layout engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for layout engineer in California is $119,266.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,800.00 and $142,100.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Layout Engineer, and why are they important?

To thrive as a Layout Engineer, you need a solid background in electrical engineering or a related field, along with expertise in CMOS technology and semiconductor design principles. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of DRC/LVS checks is typically required. Attention to detail, problem-solving abilities, and effective collaboration skills help distinguish top performers in this role. These competencies ensure accurate and efficient circuit layouts, which are critical for the performance and manufacturability of microelectronic devices.

What are some common challenges faced by Layout Engineers when collaborating with design and verification teams?

Layout Engineers often work closely with design and verification teams to ensure that integrated circuit layouts meet design specifications and manufacturability requirements. A common challenge is balancing the need for optimal performance with physical constraints like area, power, and routing limitations. Effective communication and iterative feedback are crucial, as changes in one team's work can impact another's. Staying organized and being proactive in addressing design rule violations or timing issues can help facilitate smoother collaboration and project success.

What are layout engineers?

Layout engineers are professionals who design and create the physical layout of integrated circuits (ICs) and electronic components on semiconductor chips. They translate circuit schematics into precise geometric representations that can be manufactured on silicon wafers, ensuring that the layout meets design specifications for performance, reliability, and manufacturability. Layout engineers work closely with circuit designers and use specialized software tools to optimize the placement and routing of components. Their work is essential for producing functional, efficient, and cost-effective microchips used in various electronic devices.

What is the difference between Layout Engineer vs PCB Design Engineer?

AspectLayout EngineerPCB Design Engineer
Required CredentialsBachelor's in Electrical, Electronics, or related fields; certifications like IPC Designer Certification are commonBachelor's in Electrical Engineering or PCB Design; certifications like IPC Designer Certification are common
Work EnvironmentElectronics manufacturing, semiconductor, or integrated circuit companies; design labsElectronics manufacturing, consumer electronics, or aerospace industries; design offices
Employer & Industry UsageUsed in integrated circuit and chip design companiesUsed in PCB manufacturing and electronics product companies

While both roles involve electronic design, a Layout Engineer focuses on physical placement and routing of integrated circuits or chips, whereas a PCB Design Engineer specializes in designing printed circuit boards for electronic devices. Both roles require similar certifications and often work in related industries, but their specific focus areas differ significantly.

What are popular job titles related to Layout Engineer jobs in California? For Layout Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Layout Engineer jobs in California look for? The top searched job categories for Layout Engineer jobs in California are:
What cities in California are hiring for Layout Engineer jobs? Cities in California with the most Layout Engineer job openings:
Layout Engineer jobs near you
Infographic showing various Layout Engineer job openings in California as of May 2026, with employment types broken down into 92% Full Time, 5% Part Time, and 3% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $119,266 per year, or $57.3 per hour.
Memory Layout Engineer

Memory Layout Engineer

Pacer Group

Irvine, CA • On-site

Contractor

Posted 18 days ago

Job description

Job Title: Memory Layout Engineer
Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ)
Job Duration: 3 Months, Contract to Hire
 
Job Responsibilities: 
  • Design and implement custom memory layouts for advanced technology nodes, collaborating with circuit designers to optimize performance, power, and area.
  • Mitigate layout design effects such as N-well proximity effect, diffusion spacing effect, and length of diffusion effects.
  • Collaborate with SoC partners to develop cutting-edge SRAM and Register File layout designs.
  • Participate in design reviews, to improve the quality of memory layouts.
  • Stay up to date with the latest industry trends and developments in memory layout design.
  • Perform physical verification (LVS, DRC, ANT, etc.) and debug memory layout.
  • Leading and mentoring junior layout engineers and providing guidance on layout techniques.
  • The ability to adhere to project timelines to ensure deliveries are met according to project schedules.
  • Effectively communicate with the design team to clarify and realize the layout requirements based on the schematic design intent.
  • Must be able to effectively switch between manufacturing nodes with minimal ramp.
Qualifications:
  •  7+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes including FinFET technologies
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Excellent programming skills in languages: SKILL, Perl; Python is a plus
  • Strong fundamentals in software development
  • Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
  • Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
  • Excellent communication and interpersonal skills
Mandatory Skills:
  • Synopsys/Cadence Analog Layout Tools (Preference: 5)
  • Memory design and layout (Preference: 5)
  • Python (Preference: 2)?