As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
Senior Engineer I- Design
Chandler, AZ · On-site
This role involves RTL design, functional verification, and contributing to next-generation mixed ... Programming skills in Python; familiarity with TCL or shell scripting * Experience with industry ...
Senior Engineer I- Design
Chandler, AZ · On-site
This role involves RTL design, functional verification, and contributing to next-generation mixed ... Programming skills in Python; familiarity with TCL or shell scripting * Experience with industry ...
Senior Engineer I- Design
Chandler, AZ · On-site
This role involves RTL design, functional verification, and contributing to next-generation mixed ... Programming skills in Python; familiarity with TCL or shell scripting * Experience with industry ...
Senior Engineer I- Design
Chandler, AZ · On-site
This role involves RTL design, functional verification, and contributing to next-generation mixed ... Programming skills in Python; familiarity with TCL or shell scripting * Experience with industry ...
Principal Engineer-Design
Chandler, AZ · On-site
... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...
Principal Engineer-Design
Chandler, AZ · On-site
... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...
Principal Engineer-Design
Chandler, AZ · On-site
... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...
Principal Engineer-Design
Chandler, AZ · On-site
... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$133 - $247/hr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$133 - $247/hr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
Hardware Design Engineer
Tempe, AZ · On-site
$164K - $246K/yr
Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
Sr. Logic Design Engineer
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... RTL/Logic design using System Verilog Language * Experience with Design of Data path, Power ...
Sr. Logic Design Engineer
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... RTL/Logic design using System Verilog Language * Experience with Design of Data path, Power ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$85 - $110/hr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$85 - $110/hr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
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Design Engineer | Millwork
Scottsdale, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Quick apply
Be Seen First
Design Engineer | Millwork
Scottsdale, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Be Seen First
Design Engineer | Millwork
Scottsdale, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Quick apply
Be Seen First
Design Engineer | Millwork
Scottsdale, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Be Seen First
Design Engineer | Millwork
Phoenix, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Quick apply
Be Seen First
Design Engineer | Millwork
Phoenix, AZ · On-site
$90K - $130K/yr
Design Engineer I Millwork About the Role The Design Engineer sits at the technical center of ... Leads with judgment, not authority; a junior drafter will report into this role, and the right ...
Junior Rtl Design Engineer information
What is a junior RTL design engineer?
Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.
What are the key skills and qualifications needed to thrive as a junior RTL design engineer?
To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.
What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?
Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Junior Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related field; some certifications | Bachelor's or higher in Electrical/Electronic Engineering; certifications vary |
| Work Environment | Design teams in semiconductor or electronics companies | Design and development teams in similar industries |
| Employer & Industry Usage | Commonly employed in chip design, FPGA, ASIC development | Used in digital circuit and system design across industries |
Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.
What are popular job titles related to Junior Rtl Design Engineer jobs in Arizona?
For Junior Rtl Design Engineer jobs in Arizona, the most frequently searched job titles are:
- Aeronautical Design Engineer
- Entry Level Mechanical Design Engineer
- Nuclear Core Design Engineer
- Mechanical Design Engineer
- Remote Mechanical Design Engineer
- Associate Design Engineer
- Tool Design Engineer
- Internship Electric Motor Design Engineer
- Mechanical Engineer No Experience
- Mechanical Engineer Designer
What job categories do people searching Junior Rtl Design Engineer jobs in Arizona look for?
The top searched job categories for Junior Rtl Design Engineer jobs in Arizona are:
What cities in Arizona are hiring for Junior Rtl Design Engineer jobs?
Cities in Arizona with the most Junior Rtl Design Engineer job openings:
Full-time
Re-posted 4 days ago
Analog Devices rating
8.5
Based on 17 frontline employees who took The Breakroom Quiz
33rd of 159 rated electronics manufacturers
Job description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed-signal and power management ICs. You will apply AI/ML techniques to improve design automation, optimization, and productivity across the digital design flow. Your work will contribute to products spanning multiple business units, directly supporting how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed-signal and power management ICs. You will apply AI/ML techniques to improve design automation, optimization, and productivity across the digital design flow. Your work will contribute to products spanning multiple business units, directly supporting how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities
- Apply AI/ML methodologies to improve synthesis results, timing closure, power estimation, and design space exploration
- Develop and implement digital subsystems for mixed-signal ICs, including control logic, digital interfaces, and on-chip processing blocks
- Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
- Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal)
- Participate in architecture and design reviews, contributing technical analysis on timing, area, power, and testability trade-offs
- Collaborate with analog design teams to implement and integrate digital-analog interfaces and control architectures
- MSEE or MSCE with 7+ years of digital IC design experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
- Strong RTL design skills in Verilog/SystemVerilog with experience delivering complex digital subsystems
- Demonstrated ability to deliver digital designs through tape-out, silicon validation, and production release
- Solid scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
- Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
- Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
- Excellent presentation, technical writing, and communication skills
- Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform design workflows, with an enthusiasm for discovering more effective ways of working
- Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
- Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
- Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
- Strong analytical and problem-solving abilities
- Application of AI/ML-driven workflows to improve design quality, turnaround time, or coverage
- Block-level digital subsystem ownership from specification through silicon bring-up and production validation
- Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
- DFT implementation including scan insertion, ATPG pattern generation, and fault coverage closure
- Share AI/ML-driven improvements to digital design workflows and best practices with team members
- Work with analog design, verification, and applications teams to implement digital control architectures that meet system-level requirements
- Contribute to design reviews and cross-team technical discussions
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
What Analog Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Analog Devices
Sourced by ZipRecruiter
Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Industry
Electrical equipment, appliance, and component manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Norwood, MA, US
Year founded
1965