As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
Senior IP Design Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Developing RTL, fixing bugs, performing design checks and generating of implementation constraints ... Computer Engineering or a similar related field and experience working in design of complex ...
New
Senior IP Design Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Developing RTL, fixing bugs, performing design checks and generating of implementation constraints ... Computer Engineering or a similar related field and experience working in design of complex ...
New
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Master's degree in computer engineering, electrical engineering, or related field. * Knowledge of ...
Mechanical Design Engineer
Chandler, AZ · On-site
$74K - $101K/yr
Mechanical Design Engineer (Automation/Critical Design/SolidWorks) Are you a hands-on Mechanical ... Mentor junior designers and provide technical guidance Requirements * 10+ years of mechanical ...
Mechanical Design Engineer
Chandler, AZ · On-site
$74K - $101K/yr
Mechanical Design Engineer (Automation/Critical Design/SolidWorks) Are you a hands-on Mechanical ... Mentor junior designers and provide technical guidance Requirements * 10+ years of mechanical ...
Mechanical Design Engineer
Chandler, AZ · On-site
$100K - $130K/yr
Mechanical Design Engineer (Automation/Critical Design/SolidWorks) Are you a hands-on Mechanical ... Mentor junior designers and provide technical guidance Requirements * 10+ years of mechanical ...
Quick apply
Mechanical Design Engineer
Chandler, AZ · On-site
$100K - $130K/yr
Mechanical Design Engineer (Automation/Critical Design/SolidWorks) Are you a hands-on Mechanical ... Mentor junior designers and provide technical guidance Requirements * 10+ years of mechanical ...
Digital Design Engineer 4
Tucson, AZ · On-site
$175K/yr
Document design processes and maintain project records ... Mentor junior engineers and provide technical guidance. * Stay updated with industry trends and ...
Quick apply
Digital Design Engineer 4
Tucson, AZ · On-site
$175K/yr
Document design processes and maintain project records ... Mentor junior engineers and provide technical guidance. * Stay updated with industry trends and ...
Provide technical leadership and mentorship to junior engineers within the MCU and Edge AI ... Proficiency with EDA tools for architecture exploration, RTL design, synthesis, and physical ...
Provide technical leadership and mentorship to junior engineers within the MCU and Edge AI ... Proficiency with EDA tools for architecture exploration, RTL design, synthesis, and physical ...
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ...
New
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ...
New
The engineer will manage complex projects from concept through production, mentor junior engineers ... In addition, the Senior Connector Design Engineer will help define product specifications and ...
The engineer will manage complex projects from concept through production, mentor junior engineers ... In addition, the Senior Connector Design Engineer will help define product specifications and ...
Provide technical leadership and mentorship to junior engineers within the MCU and Edge AI ... Proficiencywith EDA tools for architecture exploration, RTL design, synthesis, and physical ...
Provide technical leadership and mentorship to junior engineers within the MCU and Edge AI ... Proficiencywith EDA tools for architecture exploration, RTL design, synthesis, and physical ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Quick apply
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Junior Rtl Design Engineer information
What engineers make $300,000 a year?
What is the salary of RTL design engineer?
What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?
What engineers make $200,000 a year?
What are Junior RTL Design Engineers?
What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Junior Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related field; some certifications | Bachelor's or higher in Electrical/Electronic Engineering; certifications vary |
| Work Environment | Design teams in semiconductor or electronics companies | Design and development teams in similar industries |
| Employer & Industry Usage | Commonly employed in chip design, FPGA, ASIC development | Used in digital circuit and system design across industries |
Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.
What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?
What engineer makes $500,000 a year?
- Junior Mechanical Design Engineer
- Work From Home Bms Design Engineer
- Internship Electric Motor Design Engineer
- Remote Work From Home Analog Mixed Signal Design Engineer
- Work From Home Gearbox Design Engineer
- Vlsi Physical Verification
- Mixed Signal Design Engineer
- Work From Home Analog Ic Design Engineer
- Analog Mixed Signal Design Engineer
- Design Engineer
Microchip Technology rating
8.1
Based on 31 frontline employees who took The Breakroom Quiz
40th of 141 rated electronics manufacturers
Job description
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
Microchip's NCS Team is seeking an experienced Design engineer to support PHY (Physical Layer) development for our next generation of USB products. The role will include working with analog and digital engineers to create mixed-signal IPs and SoC products. As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate must be in the Chandler design center.
Requirements/Qualifications:
- Bachelors degree with at least 10 years of experience in digital design with solid, hands-on experience in RTL Coding and functional verification.
- Experience in USB and Ethernet PHY protocols is a strong plus-point.
- Must have knowledge and experience in Verilog/System Verilog design and test bench creation.
- Must have excellent debug skills in both functional and gate level simulations
- Experience with Verification methodologies such as UVM/VMM is a desired skillset.
- Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT methodology, equivalence checking and synthesis.
- Hands-on experience required with Mentor and Synopsys CAD tools such as Questa, Design Compiler, Formality and Spyglass.
- Knowledge in synthesis for defining timing constraints to chip-level integration team and for supporting timing closure for sub-blocks.
- Ability to solve timing constraint challenges including asynchronous designs with multipleclock domain crossings and for synchronous designs.
- Knowledge of ASIC test methodology such as Stuck-At/At-Speed scan insertion is a plus.
- Proficiency in a scripting language such as C, TCL, Perl, Awk, UNIXshell.
- Knowledge of revision control tools such as CVS, Perforce, DesignSync, etc. and experience with tagging and release methodology
- Support chip-level integration, verification, and validation teams
- Provide design documentation, description, and information to internal customers.
- Ability to work as part of digital, analog, and DSP design team and as part of global multi-sited Development team.
- The candidate must possess good verbal and writtenskills andbe able to participate in group meetings, provide project updates, andwrite functional and technical documents.Be proactiveand be willingto learn and adapt quickly in a dynamic and cross-functional environment.
Travel Time:
0% - 25%Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:
80% sitting, 10% standing, 10% walking, 100% insideMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
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About Microchip
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Chandler, AZ, US
Year founded
1989