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Junior Rtl Design Engineer Jobs in Phoenix, AZ (NOW HIRING)

Broadcom, Inc.

RTL Design Engineer

Chandler, AZ · On-site

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

Intel

RTL Design Engineer

Phoenix, AZ

$105.65K - $200.34K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...

Broadcom

RTL Design Engineer

Chandler, AZ

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

Intel

Senior RTL Design Engineer

Phoenix, AZ · On-site

The Role and Impact As a Senior RTL Design Engineer, you will play a pivotal role in developing Intel's next-generation microprocessors, contributing to groundbreaking technologies that drive ...

Cirrus Logic

Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Cirrus Logic

Senior Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Cirrus Logic

Staff Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Intel

Lead CPU Design Engineer

Phoenix, AZ

Resolve failing RTL tests by implementing corrective measures, ensuring feature correctness and functionality. * Document micro architectural specifications (MAS) for CPU features. * Support SoC ...

Intel Corporation

Lead CPU Design Engineer

Phoenix, AZ · On-site

Resolve failing RTL tests by implementing corrective measures, ensuring feature correctness and functionality. * Document micro architectural specifications (MAS) for CPU features. * Support SoC ...

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Junior Rtl Design Engineer information

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$33.3K

$71.3K

$108.7K

How much do junior rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for junior rtl design engineer in Phoenix, AZ is $71,290.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,200.00 and $79,400.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Phoenix, AZ? For Junior Rtl Design Engineer jobs in Phoenix, AZ, the most frequently searched job titles are:
What job categories do people searching Junior Rtl Design Engineer jobs in Phoenix, AZ look for? The top searched job categories for Junior Rtl Design Engineer jobs in Phoenix, AZ are:
Junior Rtl Design Engineer jobs near you
RTL Design Engineer

RTL Design Engineer

Broadcom, Inc.

Chandler, AZ • On-site

$127.10K - $203.40K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 8 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers

Job description

Please Note:
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2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.
  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/SystemVerilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Job Requirements
  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications
  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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