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Junior Rtl Design Engineer Jobs in Phoenix, AZ (NOW HIRING)

FPGA Engineer (Space)

Tempe, AZ · On-site

$129K - $194K/yr

What you'll do As a FPGA Engineer on the Space Infrastructure team, you will design, implement, and ... Contribute to architecture, design, and implementation of FPGA based digital systems * Develop RTL ...

Senior Digital Engineer

Chandler, AZ · On-site

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ...

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ...

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ...

RF Design Engineer

Chandler, AZ

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Mentor junior engineers and support internal concurrent design efforts while contributing to design standards, manufacturability considerations, and internal review processes. * Generate required ...

Review and, as assigned, supervise the project work of junior engineers. * Perform other duties as required. #LI-TM1 #LI-Hybrid Skills & Abilities * Strong knowledge of electrical engineering design ...

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

  • Medical

  • Retirement

  • PTO

Technical Leadership • Lead analog design projects from specification to silicon validation. • Mentor junior engineers and provide technical guidance. • Collaborate with cross-functional teams ...

Senior Mechanical Design Engineer

Chandler, AZ · On-site

$89K - $123K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Senior Mechanical Design Engineer (Automation / Critical Design / SolidWorks) Design the Next ... Mentor junior engineers and help establish engineering standards and best practices. Required ...

Senior Analog Design Engineer

Phoenix, AZ

$200K/yr

  • Medical

  • Retirement

  • PTO

Mentor junior engineers and provide technical guidance. Collaborate with cross-functional teams including architecture, logic, verification, physical design, layout, post-silicon manufacturing and ...

Senior Analog Design Engineer

Phoenix, AZ · On-site

$190.61 - $269.10/hr

  • Medical

  • Retirement

  • PTO

Technical Leadership • Lead analog design projects from specification to silicon validation. • Mentor junior engineers and provide technical guidance. • Collaborate with cross-functional teams ...

Senior Mechanical Design Engineer

Chandler, AZ · On-site

$89K - $123K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Senior Mechanical Design Engineer (Automation / Critical Design / SolidWorks) Design the Next ... Mentor junior engineers and help establish engineering standards and best practices. Required ...

RF Design Engineer

Chandler, AZ · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Mentor junior engineers and support internal concurrent design efforts while contributing to design standards, manufacturability considerations, and internal review processes. * Generate required ...

Showing results 41-60

Junior Rtl Design Engineer information

See Phoenix, AZ salary details

$33.3K

$71.3K

$108.7K

How much do junior rtl design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for junior rtl design engineer in Phoenix, AZ is $71,290.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,200.00 and $79,400.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

FPGA Engineer (Space)

Viasat, Inc.

Tempe, AZ • On-site

$129K - $194K/yr

Full-time

Re-posted 29 days ago


Viasat rating

6.3

Company rating: 6.3 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

78th of 99 rated telecommunications companies


Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.


What you'll do

As a FPGA Engineer on the Space Infrastructure team, you will design, implement, and deliver high speed signal-processing algorithms, cryptography, and/or network protocols in FPGAs. You will be involved in the full design phase, starting from the requirements phase to documentation, block diagrams, implementation of source code, simulation, place and route, testing in hardware, and integration. You will assist other engineers from different fields and must be capable of working in both a small team setting and a larger team setting. You will be able to use your engineering knowledge to support the next generation of advanced communications products and systems


The day-to-day
  • Contribute to architecture, design, and implementation of FPGA based digital systems
  • Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions
  • Integrate and deploy designs on FPGA and FPGA SoC platforms
  • Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
  • Support bring up, integration, and debug in the lab using logic analyzers, scopes, and other instrumentation
  • Participate in system level trade studies, FPGA utilization, design and code reviews
  • Maintain and control FPGA code revision history
  • Create clear documentation and support test, validation, and production efforts
  • Work autonomously with little instruction to solve well-defined problems

What you'll need
  • Bachelor Degree in Electrical Engineering, Computer Engineering or a related field
  • 2+ years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog and/or VHDL
  • Experience with RTL design for various signal processing blocks
  • Experience designing and coding for re-use, maintainability and scalability
  • Ability to read schematics and work closely with hardware design teams
  • Good oral and written communications skills
  • US citizenship
  • Ability to travel up to 10%

What will help you on the job
  • MSEE degree preferred
  • Experience with lab equipment including logic analyzers, DMM, spectrum analyzers
  • Experience with high-speed interfaces like SERDES, DDR2/3/4, LVDS
  • Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify
  • Familiarity with TCL, Perl, Python or another scripting language
  • Familiarity with FPGA modules simulation and testbench development
  • Experience and familiarity with Linux-based development environments
  • Experience with GitHub
    • Experience with Matlab
  • Familiarity with CI/CD practices
    • Familiarity with AI Agents (Claud Code, Copilot, etc.)
  • Strong troubleshooting skills
  • Understanding and knowledge of Satellite communication waveforms and standards

Salary range
$104,500.00 - $164,500.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $129,000.00- $194,000.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

Qualifications:
  • Bachelor Degree in Electrical Engineering, Computer Engineering or a related field
  • 2+ years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog and/or VHDL
  • Experience with RTL design for various signal processing blocks
  • Experience designing and coding for re-use, maintainability and scalability
  • Ability to read schematics and work closely with hardware design teams
  • Good oral and written communications skills
  • US citizenship
  • Ability to travel up to 10%
Education:UNAVAILABLEEmployment Type: FULL_TIME

What Viasat employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


ViaSat logo

About ViaSat

Sourced by ZipRecruiter

At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.

Industry

Telecommunications

Company size

5,001 - 10,000 Employees

Headquarters location

Carlsbad, CA, US

Year founded

1986