Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team. * Collaborate ...
Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team. * Collaborate ...
DFT engineer with 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. * Self-driven, results-oriented with a positive outlook, and a clear ...
DFT engineer with 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. * Self-driven, results-oriented with a positive outlook, and a clear ...
Principal DFT Engineer
Austin, TX · On-site
DFT engineer with 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. * Self-driven, results-oriented with a positive outlook, and a clear ...
Principal DFT Engineer
Austin, TX · On-site
DFT engineer with 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. * Self-driven, results-oriented with a positive outlook, and a clear ...
ASIC DFT Engineer
Irvine, CA · On-site
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
Quick apply
ASIC DFT Engineer
Irvine, CA · On-site
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
JTAG * C Language * UART * Embedded systems * SPI * Boot and application layer development * USB * SW Unit Testing * Automotive
JTAG * C Language * UART * Embedded systems * SPI * Boot and application layer development * USB * SW Unit Testing * Automotive
Proficiency with debugging tools (JTAG, GDB, oscilloscopes, logic analyzers). Experience with version control (Git) and CI/CD pipelines.
Proficiency with debugging tools (JTAG, GDB, oscilloscopes, logic analyzers). Experience with version control (Git) and CI/CD pipelines.
Embedded Software Engineer (RTOS / ARM / Drivers)
Spring, TX · On-site
$117K - $154K/yr
Git / GitHub Technologies C, C++, FreeRTOS, ARM, Linux, JTAG/SWD, UART, I2C, SPI
Quick apply
Embedded Software Engineer (RTOS / ARM / Drivers)
Spring, TX · On-site
$117K - $154K/yr
Git / GitHub Technologies C, C++, FreeRTOS, ARM, Linux, JTAG/SWD, UART, I2C, SPI
Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team. * Collaborate ...
Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team. * Collaborate ...
Sr Test Embedded Engineer - VSE
Plano, TX · On-site
Experience with testing tools and frameworks (e.g., LabVIEW, JTAG, etc.) and automated testing methodologies. * Knowledge of communication protocols (e.g., I2C, SPI, UART) and hardware interfaces.
Quick apply
Sr Test Embedded Engineer - VSE
Plano, TX · On-site
Experience with testing tools and frameworks (e.g., LabVIEW, JTAG, etc.) and automated testing methodologies. * Knowledge of communication protocols (e.g., I2C, SPI, UART) and hardware interfaces.
Sr. IO Design Engineer - SoC & TAP Innovation (Chandler)
Chandler, AZ · On-site
$102K - $140K/yr
You will work in a dynamic team on advanced technologies, applying your expertise in design planning and JTAG integration. Candidates should hold a B.S or M.S in electrical engineering and have over ...
Sr. IO Design Engineer - SoC & TAP Innovation (Chandler)
Chandler, AZ · On-site
$102K - $140K/yr
You will work in a dynamic team on advanced technologies, applying your expertise in design planning and JTAG integration. Candidates should hold a B.S or M.S in electrical engineering and have over ...
DFT Engineer (Only W2)
Santa Clara, CA · On-site
Implement MBIST and/or Boundary Scan (BSCAN, JTAG) * Support DFT architecture and chip-level integration * Debug DFT issues and improve test coverage Requirements: * Experience in at least 2 DFT ...
DFT Engineer (Only W2)
Santa Clara, CA · On-site
Implement MBIST and/or Boundary Scan (BSCAN, JTAG) * Support DFT architecture and chip-level integration * Debug DFT issues and improve test coverage Requirements: * Experience in at least 2 DFT ...
FreeRTOS Engineer
Seattle, WA · On-site
$149K - $197K/yr
Conduct low-level debugging using tools such as JTAG, oscilloscopes, and logic analyzers * Support integration of communication protocols such as CAN and LIN * Participate in design reviews ...
FreeRTOS Engineer
Seattle, WA · On-site
$149K - $197K/yr
Conduct low-level debugging using tools such as JTAG, oscilloscopes, and logic analyzers * Support integration of communication protocols such as CAN and LIN * Participate in design reviews ...
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
Senior IO Design Engineer - Lead Next‑Gen Storage SoC (Chandler)
Chandler, AZ · On-site
$102K - $140K/yr
Responsibilities include design planning, IO cell placement, and working on JTAG TAP controller integration. The position offers robust compensation and growth opportunities within a dynamic team. #J ...
Senior IO Design Engineer - Lead Next‑Gen Storage SoC (Chandler)
Chandler, AZ · On-site
$102K - $140K/yr
Responsibilities include design planning, IO cell placement, and working on JTAG TAP controller integration. The position offers robust compensation and growth opportunities within a dynamic team. #J ...
SoC DFT Engineer
Austin, TX · On-site
Preferred Qualifications Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time. Experience developing DFT ...
SoC DFT Engineer
Austin, TX · On-site
Preferred Qualifications Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time. Experience developing DFT ...
Embedded Engineer
$118K - $156K/yr
Debug board-level and system-level issues using tools such as oscilloscopes, logic analyzers, and JTAG debuggers. * Collaborate closely with hardware engineers to investigate and resolve hardware ...
Quick apply
Embedded Engineer
$118K - $156K/yr
Debug board-level and system-level issues using tools such as oscilloscopes, logic analyzers, and JTAG debuggers. * Collaborate closely with hardware engineers to investigate and resolve hardware ...
DFT Engineer
Santa Clara, CA · On-site
Work on Scan insertion, ATPG, GLS (timing/non-timing) Implement MBIST and/or Boundary Scan (BSCAN, JTAG) Support DFT architecture and chip-level integration Debug DFT issues and improve test coverage ...
Quick apply
DFT Engineer
Santa Clara, CA · On-site
Work on Scan insertion, ATPG, GLS (timing/non-timing) Implement MBIST and/or Boundary Scan (BSCAN, JTAG) Support DFT architecture and chip-level integration Debug DFT issues and improve test coverage ...
Hardware Debug Engineer
Seattle, WA · On-site
$140K - $185K/yr
Experience using Oscilloscopes, Power supplies, Signal generators, JTAG debugger (ITP), Thermal tools, DMM, Microscopes, Camera, and Soldering station * Strong organizational, communication ...
Quick apply
Hardware Debug Engineer
Seattle, WA · On-site
$140K - $185K/yr
Experience using Oscilloscopes, Power supplies, Signal generators, JTAG debugger (ITP), Thermal tools, DMM, Microscopes, Camera, and Soldering station * Strong organizational, communication ...
Firmware Engineer
Menlo Park, CA · On-site
... JTAG/SWD. • Develop secure bootloaders and update soluions • Write and maintain unit tests and automated test scripts for firmware validation. • Collaborate with cross-functional teams ...
Firmware Engineer
Menlo Park, CA · On-site
... JTAG/SWD. • Develop secure bootloaders and update soluions • Write and maintain unit tests and automated test scripts for firmware validation. • Collaborate with cross-functional teams ...
SoC DFT Engineer
Austin, TX · On-site
Preferred Qualifications Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time. Experience developing DFT ...
SoC DFT Engineer
Austin, TX · On-site
Preferred Qualifications Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time. Experience developing DFT ...
Jtag information
See salary details
$33.17 - $44.21
4% of jobs
$44.21 - $55.24
6% of jobs
$55.24 - $66.28
14% of jobs
$66.66 is the 25th percentile. Wages below this are outliers.
$66.28 - $77.32
23% of jobs
The median wage is $78.52 / hr.
$77.32 - $88.35
24% of jobs
$91.34 is the 75th percentile. Wages above this are outliers.
$88.35 - $99.39
13% of jobs
$99.39 - $110.42
3% of jobs
$110.42 - $121.46
5% of jobs
$121.46 - $132.50
3% of jobs
$132.50 - $143.53
1% of jobs
$143.53 - $154.57
3% of jobs
$33
$85
$154
How much do jtag jobs pay per hour?
What is the difference between Jtag vs Test Technician?
| Aspect | Jtag | Test Technician |
|---|---|---|
| Required Credentials | Typically certifications in electronics or hardware testing, some may have JTAG-specific training | Often holds certifications in electronics, testing, or quality assurance |
| Work Environment | Hardware development labs, manufacturing facilities, electronics testing environments | Manufacturing plants, quality control labs, electronics assembly lines |
| Industry Usage | Used for debugging, programming, and testing hardware via JTAG interface | Performs testing, troubleshooting, and quality checks on electronic products |
Jtag specialists focus on hardware testing and debugging using JTAG interfaces, while Test Technicians perform broader testing and quality assurance tasks. Both roles require electronics knowledge, but Jtag roles are more specialized in hardware debugging techniques.
What are some common challenges encountered when working as a JTAG engineer, and how can they be addressed?
Is JTAG still used?
What jobs pay 4000 a week without a degree?
What are the key skills and qualifications needed to thrive as a JTAG (Joint Test Action Group) Engineer, and why are they important?
What are JTAG engineers?
What are some unique J starting jobs?
What can you do with JTAG?
- Microcontroller
- Internship Remote Electronic Technician
- Remote Navy Electronics Technician Civilian
- Digital Electronics Engineers
- Entry Level Electronic Circuit Design
- Phd Power Electronic Research Engineer
- Electronics Engineer Entry
- Associate Electronics Technician
- Remote Chickasaw Nation
- Electronics Technician Manager

Senior Technical Staff Engineer - Design (IO) (Chandler)
Chandler, AZ • On-site
Full-time
Medical, Retirement
Posted 9 days ago
Microchip Technology rating
8.0
Based on 32 frontline employees who took The Breakroom Quiz
46th of 142 rated electronics manufacturers
Job description
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job DescriptionThe successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.
An opening exists for Tech Staff/Sr. Staff IO Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!
As a Staff/Sr.Staff Design Engineer, your job will entail the following:
- Design planning of pad rings and package substrates, bump pattern construction.
- Dynamically define and optimize pad ring connectivity.
- Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,)
- Interface with and support Architect, PD, PE, technology development and foundries teams.
- Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team.
- Collaborate with CFTs on TAP controller operation, scan-enable path handling, and post-silicon debug requirements.
- Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds.
- B.S or M.S degree in electrical engineering with 12+ years related experience.
- Hands‑on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
- Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
- Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
- Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand‑off).
- Experience with Verilog/System Verilog is required.
- Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation.
- Hands‑on experience with DFT methodologies is a plus and considered equivalent familiarity.
- Familiarity with JTAG-based post‑silicon debug flows and bring‑up strategies for SoC IO validation.
- Experience with boundary scan cell behavior and test access port (TAP) signal verification is a plus.
- Scripting experience or knowledge is a plus.
- Excellent analytical, communication (written and verbal), and documentation skills.
0% - 25%
Physical AttributesHearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements80% sitting, 10% standing, 10% walking, 100% inside
Pay RangeWe offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below.
The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.*
- Range is dependent on numerous factors including job location, skills and experience.
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agenciesMicrochip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
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About Microchip
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Chandler, AZ, US
Year founded
1989