We are looking for a DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest ...
We are looking for a DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest ...
We are looking for a DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest ...
New
We are looking for a DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest ...
New
C/C++ Engineer (Aerospace)
Brea, CA · On-site
C,C++,QT,QML, Qt Creator, Qt Quick framework, RTOS, CAN, SPI, I2C, UART, ARINC 429, control systems, Git, In Flight Entertainment, GDB, JTAG, Logic Analyzers * Experience: 6 to 15 Years * Good Design ...
Quick apply
C/C++ Engineer (Aerospace)
Brea, CA · On-site
C,C++,QT,QML, Qt Creator, Qt Quick framework, RTOS, CAN, SPI, I2C, UART, ARINC 429, control systems, Git, In Flight Entertainment, GDB, JTAG, Logic Analyzers * Experience: 6 to 15 Years * Good Design ...
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation , along with the ability to lead cross ...
Quick apply
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation , along with the ability to lead cross ...
Principal SoC DFT Engineer
San Jose, CA · On-site
$159K - $296K/yr
JTAG insertion and connectivity * High-speed analog/mixed signal IP integration * Execute DFT verification, debug, and DFT DRC closure * Identify, debug, and resolve DFT rule violations at both block ...
Principal SoC DFT Engineer
San Jose, CA · On-site
$159K - $296K/yr
JTAG insertion and connectivity * High-speed analog/mixed signal IP integration * Execute DFT verification, debug, and DFT DRC closure * Identify, debug, and resolve DFT rule violations at both block ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
Hardware Test Engineer - Mixed-Signal Validation | Morrisville, NC 27560 (Onsite)
Morrisville, NC · On-site
$60 - $64/hr
Proven ability to troubleshoot and debug digital interfaces (e.g., JTAG)
Quick apply
Hardware Test Engineer - Mixed-Signal Validation | Morrisville, NC 27560 (Onsite)
Morrisville, NC · On-site
$60 - $64/hr
Proven ability to troubleshoot and debug digital interfaces (e.g., JTAG)
Proficiency in debugging embedded software systems and familiarity with JTAG and ETM Trace tools.Proficient in Python and shell scripting. Excellent problem-solving and analytical thinking skills.
Proficiency in debugging embedded software systems and familiarity with JTAG and ETM Trace tools.Proficient in Python and shell scripting. Excellent problem-solving and analytical thinking skills.
Lead ASIC DFT Engineer - Remote
San Jose, CA · On-site +1
$192K/yr
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
Lead ASIC DFT Engineer - Remote
San Jose, CA · On-site +1
$192K/yr
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
JTAG and HS Analog/mixed signal IP IOBIST integration * ATPG pattern generation and coverage analysis * Proven ability to resolve DFT DRCs, connectivity issues, and testability problems * Strong TCL ...
JTAG and HS Analog/mixed signal IP IOBIST integration * ATPG pattern generation and coverage analysis * Proven ability to resolve DFT DRCs, connectivity issues, and testability problems * Strong TCL ...
Skilled in debugging embedded software systems and familiarity with JTAG and ETM Trace tools.Skilled in Python and shell scripting. Good problem-solving and analytical thinking skills. Debugging ...
Skilled in debugging embedded software systems and familiarity with JTAG and ETM Trace tools.Skilled in Python and shell scripting. Good problem-solving and analytical thinking skills. Debugging ...
Staff Embedded Software Engineer
Boston, MA · On-site
$142K - $187K/yr
Debug and troubleshoot embedded systems using tools such as GDB, JTAG, and logic analyzers. * Participate in customer engagements to gather requirements and usability criteria. Qualifications * BS ...
Staff Embedded Software Engineer
Boston, MA · On-site
$142K - $187K/yr
Debug and troubleshoot embedded systems using tools such as GDB, JTAG, and logic analyzers. * Participate in customer engagements to gather requirements and usability criteria. Qualifications * BS ...
Staff Embedded Software Engineer
Mountain View, CA · On-site
$155K - $204K/yr
Debug and troubleshoot embedded systems using tools such as GDB, JTAG, and logic analyzers. * Participate in customer engagements to gather requirements and usability criteria. Qualifications * BS ...
Staff Embedded Software Engineer
Mountain View, CA · On-site
$155K - $204K/yr
Debug and troubleshoot embedded systems using tools such as GDB, JTAG, and logic analyzers. * Participate in customer engagements to gather requirements and usability criteria. Qualifications * BS ...
FPGA Engineer
$58 - $63/hr
Program FPGA devices using JTAG interfaces * Execute validation testing on FPGA evaluation boards * Debug hardware and FPGA issues using lab equipment * Utilize oscilloscopes, logic analyzers, and ...
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FPGA Engineer
$58 - $63/hr
Program FPGA devices using JTAG interfaces * Execute validation testing on FPGA evaluation boards * Debug hardware and FPGA issues using lab equipment * Utilize oscilloscopes, logic analyzers, and ...
JTAG * SCAN * MBIST * High Speed IO
JTAG * SCAN * MBIST * High Speed IO
FPGA Engineer
Wilmington, MA · On-site
$58 - $63/hr
Program FPGA devices using JTAG interfaces * Execute validation testing on FPGA evaluation boards * Debug hardware and FPGA issues using lab equipment * Utilize oscilloscopes, logic analyzers, and ...
FPGA Engineer
Wilmington, MA · On-site
$58 - $63/hr
Program FPGA devices using JTAG interfaces * Execute validation testing on FPGA evaluation boards * Debug hardware and FPGA issues using lab equipment * Utilize oscilloscopes, logic analyzers, and ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests * ATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDF * Work with backend team ...
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Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests * ATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDF * Work with backend team ...
Senior Developer Tools Engineer
Santa Clara, CA · On-site
$143K - $189K/yr
... JTAG) and object file formats (ELF, COFF). • Collaborate with internal engineering teams to understand their needs and iterate on tooling, with a path toward external customer-facing tools.
Senior Developer Tools Engineer
Santa Clara, CA · On-site
$143K - $189K/yr
... JTAG) and object file formats (ELF, COFF). • Collaborate with internal engineering teams to understand their needs and iterate on tooling, with a path toward external customer-facing tools.
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
Jtag information
See salary details
$33.17 - $44.21
4% of jobs
$44.21 - $55.24
6% of jobs
$55.24 - $66.28
14% of jobs
$66.66 is the 25th percentile. Wages below this are outliers.
$66.28 - $77.32
23% of jobs
The median wage is $78.52 / hr.
$77.32 - $88.35
24% of jobs
$91.34 is the 75th percentile. Wages above this are outliers.
$88.35 - $99.39
13% of jobs
$99.39 - $110.42
3% of jobs
$110.42 - $121.46
5% of jobs
$121.46 - $132.50
3% of jobs
$132.50 - $143.53
1% of jobs
$143.53 - $154.57
3% of jobs
$33
$85
$154
How much do jtag jobs pay per hour?
What is the difference between Jtag vs Test Technician?
| Aspect | Jtag | Test Technician |
|---|---|---|
| Required Credentials | Typically certifications in electronics or hardware testing, some may have JTAG-specific training | Often holds certifications in electronics, testing, or quality assurance |
| Work Environment | Hardware development labs, manufacturing facilities, electronics testing environments | Manufacturing plants, quality control labs, electronics assembly lines |
| Industry Usage | Used for debugging, programming, and testing hardware via JTAG interface | Performs testing, troubleshooting, and quality checks on electronic products |
Jtag specialists focus on hardware testing and debugging using JTAG interfaces, while Test Technicians perform broader testing and quality assurance tasks. Both roles require electronics knowledge, but Jtag roles are more specialized in hardware debugging techniques.
What are some common challenges encountered when working as a JTAG engineer, and how can they be addressed?
What are the disadvantages of JTAG?
What is JTAG used for?
What jobs pay 2000 a day?
What are the key skills and qualifications needed to thrive as a JTAG (Joint Test Action Group) Engineer, and why are they important?
What are JTAG engineers?
What are some unique J starting jobs?
- Phd Power Electronic Research Engineer
- Internship Remote Electronic Technician
- Remote Navy Electronics Technician Civilian
- Digital Electronics Engineers
- Entry Level Electronic Circuit Design
- Remote Electronics
- Medical Electronics Engineering
- Electronics Engineer Entry
- Automation Electronics
- Power Electronics Hardware Engineer

DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test
Advanced Micro Devices, IncAustin, TX • On-site
$135K/yr
Full-time
Posted 3 days ago
Advanced Micro Devices rating
8.4
Based on 7 frontline employees who took The Breakroom Quiz
22nd of 139 rated electronics manufacturers
Job description
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are looking for a DFT Hardware Test Engineer/ Architect- JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest standards of quality and reliability. In this role, you'll partner closely with design, manufacturing, and quality teams to shape how our boards are validated, influence decisions that improve product robustness, and help streamline how we bring complex hardware to market. You'll contribute to an environment that values curiosity, clear communication, and continuous improvement-making a direct impact on how efficiently and confidently we deliver products to customers.
THE PERSON:
A clear, collaborative communicator who partners effectively across teams. They bring strong analytical thinking, disciplined problem solving, and calm, methodical troubleshooting under pressure. Highly organized and detail-oriented, they document and present findings succinctly, manage priorities well, and drive issues to resolution. They adapt quickly, embrace continuous improvement, and build trust through reliability, integrity, and a quality-focused mindset.
KEY RESPONSIBILITIES:
- Collaborate with hardware design teams to integrate DFT features early and ensure board-level testability.
- Develop and maintain Functional Test fixtures and Tests.
- Develop, debug, and optimize JTAG boundary scan test programs (e.g., XJTAG, Corelis, ASSET InterTech) for interconnect, memory, and device programming.
- Troubleshoot and root-cause boundary scan test failures.
- Develop and maintain ICT programs on platforms such as Teradyne and Keysight, including fixture design and optimization.
- Generate ICT test programs for analog, digital, and mixed-signal circuits, and troubleshoot ICT failures.
- Work with manufacturing teams to refine ICT processes and improve yields.
- Analyze test coverage metrics, identify improvement areas, and implement strategies to increase coverage and reduce escapes.
- Partner with design and manufacturing to resolve testability issues.
- Create and maintain test documentation including test plans, procedures, and reports; present results and track key metrics (coverage, yield, failure rates).
- Stay current on test technologies, drive process improvements, and participate in continuous improvement initiatives.
PREFERRED EXPERIENCE:
- Deep understanding of DFT principles, boundary-scan methodologies, and ICT development.
- Hands-on experience with JTAG tools (e.g., XJTAG, Corelis, ASSET InterTech) and ICT platforms (e.g., Teradyne, Keysight).
- Demonstrated ability to analyze and improve test coverage and troubleshoot complex board-level failures.
- Proficiency in scripting (Python, Perl) to automate test flows and enhance efficiency.
- Familiarity with IPC standards, PCB manufacturing practices, and failure-analysis techniques.
- Comfortable working cross-functionally in fast-paced engineering environments, driving quality and testability improvements.
ACADEMIC CREDENTIALS
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is preferred.
This role is not eligible for visa sponsorship.
#LI-BM1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US