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Ip Design Verification Engineer Jobs (NOW HIRING)

7Rays Semiconductors

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

We are seeking a highly motivated Design Verification Engineer to join our Interface IP DV team . In this role, you will collaborate closely with architects, designers, and external vendors to ensure ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases ...

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years ... IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group ... complex IP and subsystem designs, working closely with multi-functional teams throughout the ...

Apple

Design Verification Engineer

Waltham, MA · On-site

$146K - $179K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Develop directed and random verification tests to validate block and IP functionality * Develop ...

Apple

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...

Apple

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group ... complex IP and subsystem designs, working closely with multi-functional teams throughout the ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Apple

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Sivaltech

Senior Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

... design verification (chip-level or IP-level) - Strong expertise in: - SystemVerilog/UVM - Verilog/VHDL - AMBA (AHB, APB, etc.) - USB, I2C, UART, and other standard interfaces - Proficiency in ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Develop directed and random verification tests to validate block and IP functionality * Develop ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

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All JobsIp Design Verification Engineer Jobs

Ip Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do ip design verification engineer jobs pay per year?

As of Jul 12, 2026, the average yearly pay for ip design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges IP Design Verification Engineers face when working on complex SoC projects?

IP Design Verification Engineers often encounter challenges such as managing verification of increasingly complex IP blocks within tight project timelines, ensuring thorough coverage, and integrating third-party IPs seamlessly into the system-on-chip (SoC) environment. Effective communication with both design and software teams is critical to resolve functional ambiguities and debug issues rapidly. Additionally, keeping up with evolving verification methodologies and tools, such as UVM and SystemVerilog, is essential for delivering high-quality, robust IP in a fast-paced environment.

What are the key skills and qualifications needed to thrive as an IP Design Verification Engineer, and why are they important?

To thrive as an IP Design Verification Engineer, you need a strong background in digital design concepts, hardware description languages (HDLs) like Verilog or VHDL, and a degree in electrical engineering or a related field. Familiarity with verification methodologies such as UVM, simulation tools like Synopsys VCS or Cadence Incisive, and scripting languages such as Python or Perl is typically required. Analytical thinking, strong problem-solving abilities, and effective communication skills help engineers collaborate and resolve complex design issues efficiently. These skills are essential to ensure that IP blocks function correctly, meet specifications, and integrate seamlessly into larger systems.

What is the difference between Ip Design Verification Engineer vs Ip Validation Engineer?

AspectIp Design Verification EngineerIp Validation Engineer
Primary FocusVerifying the correctness and functionality of IP designs before tape-outValidating IPs in real-world or system environments post-design
Work EnvironmentDesign teams, simulation, and verification toolsTesting labs, system integration, and validation platforms
Required CredentialsBachelor's or master's in Electrical Engineering or related field; knowledge of verification languagesBachelor's or master's in Electrical Engineering; experience with validation and testing methodologies

While both roles involve working with IPs, the Ip Design Verification Engineer focuses on verifying the design correctness during development, whereas the Ip Validation Engineer tests the IPs in real-world scenarios after design completion. Both roles are essential in the chip development process and often collaborate closely.

What does an IP Design Verification Engineer do?

An IP Design Verification Engineer is responsible for ensuring that integrated circuit (IC) intellectual property (IP) blocks function correctly and meet design specifications before manufacturing. They create and execute comprehensive test plans, develop simulation environments, and use various verification methodologies such as UVM (Universal Verification Methodology) to identify and resolve design issues. Their work is crucial for catching design flaws early, reducing costly errors, and ensuring overall product quality. By collaborating closely with design engineers and other teams, they help deliver reliable and high-performance hardware solutions.
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What job categories do people searching Ip Design Verification Engineer jobs look for? The top searched job categories for Ip Design Verification Engineer jobs are:
Ip Design Verification Engineer jobs near you
Infographic showing various Ip Design Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer - Interface IP

Etched

San Jose, CA • On-site

$150K - $275K/yr

Full-time

Medical, Dental, Vision

Re-posted 3 days ago

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

  • Understand vendor IP configurations and handle handshake with internal IP team

  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

  • 5+ years of design verification experience

  • You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

  • You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

  • You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

  • You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

  • You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

  • Experience handling vendors and integration of IP/VIP’s

  • UVM/System Verilog

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2k per month for those living within walking distance of the office

  • Relocation support for those moving to San Jose (Santana Row)

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Compensation Range: $150K - $275K