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Internship Serdes Design Engineer Jobs in Tempe, AZ

Alphacore Inc

Analog Layout Design Engineer

Tempe, AZ · On-site

$193.50K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona ... Execute analog layout design of key circuits such as PLLs, ADCs, and SerDes * Work on advanced ...

Alphacore Inc

Analog Layout Design Engineer

Tempe, AZ · On-site +1

$196.60K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona ... Execute analog layout design of key circuits such as PLLs, ADCs, and SerDes * Work on advanced ...

Marvell

Package Design Engineer

Chandler, AZ

$133.90K/yr

Meet specifications for high-speed interfaces such as HBM, DDR, PCIe and 56G/112G SerDes. * 2.5D ... every stage - from internship to retirement and through life's most important moments. Our ...

Marvell

Advanced Packaging Design

Chandler, AZ

$133.90K/yr

What You Can Expect As an Advanced Packaging Design engineer, responsibilities include ... Experience with developing solutions with high-speed interfaces such as HBM, DDR, SERDES, PCIe and ...

Intel

Lead CPU Design Engineer

Phoenix, AZ

... internship experiences Minimum Qualifications: * Bachelor's degree in Electrical Engineering ... Logic design and RTL coding techniques. Expertise in power and performance analysis and ...

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How much do internship serdes design engineer jobs pay per hour?

As of May 27, 2026, the average hourly pay for internship serdes design engineer in Tempe, AZ is $18.56, according to ZipRecruiter salary data. Most workers in this role earn between $13.80 and $20.72 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship Serdes Design Engineer, and why are they important?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an Internship Serdes Design Engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What does an Internship Serdes Design Engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

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Internship Serdes Design Engineer jobs near you

SerDes Architect and Design Engineer

Chelsea Search Group

Phoenix, AZ

$189.30K/yr

Full-time

Posted 3 days ago

Job description

SerDes Architect and Design Engineer
Responsibilities:
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Design high-performance analog/mixed-signal circuits in advanced node technologies 
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
Required Skills & Experience:
• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Strong communication and documentation skills