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Internship Ic Layout Mask Designer Jobs (NOW HIRING)

Sr IC Digital Layout Designer

Irvine, CA · Hybrid

$130K - $160K/yr

Key Responsibilities Develop and execute full-chip and block-level physical layout for advanced digital and mixed-signal IC designs. Work with circuit designers to interpret schematics and ensure ...

... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.

QCT WAN RFIC design group is seeking an experienced Mask Layout Designer to fulfill both block and project lead level roles working in a very large team environment. Responsibilities will vary ...

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

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Internship Ic Layout Mask Designer information

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How much do internship ic layout mask designer jobs pay per hour?

As of Jul 23, 2026, the average hourly pay for internship ic layout mask designer in the United States is $16.33, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.

What does an Internship IC Layout Mask Designer do?

An Internship IC Layout Mask Designer assists in creating detailed layouts for integrated circuit (IC) chips using specialized design software. They work under the supervision of experienced engineers to translate circuit schematics into physical layouts, ensuring that all design rules and manufacturing requirements are met. Interns may also help with design checks, participate in design reviews, and learn about semiconductor manufacturing processes. This role provides hands-on experience in the microelectronics industry, helping interns develop technical and teamwork skills relevant to IC design.

What is the difference between Internship Ic Layout Mask Designer vs IC Design Engineer?

AspectInternship Ic Layout Mask DesignerIC Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, VLSI Design, or similar
Work EnvironmentDesign labs, CAD software, collaborative teamsDesign teams, simulation tools, project-based
Industry UsageFoundries, semiconductor companies, research labsSemiconductor companies, integrated circuit firms
Search & ComparisonOften compared for entry-level roles and trainingMore advanced, focused on full chip design

The Internship Ic Layout Mask Designer role focuses on creating physical layouts for semiconductor masks, often as an entry-level position. In contrast, an IC Design Engineer handles the entire chip design process, requiring more experience and advanced skills. Both roles are essential in the semiconductor industry but differ mainly in scope and experience level.

What are the key skills and qualifications needed to thrive as an Internship IC Layout Mask Designer, and why are they important?

Success as an Internship IC Layout Mask Designer requires a foundation in electrical engineering or a related field, strong understanding of semiconductor physics, and basic knowledge of IC design principles. Familiarity with EDA tools such as Cadence Virtuoso or Synopsys, as well as an understanding of design rule checking (DRC) and layout versus schematic (LVS) verification, is highly valuable. Attention to detail, problem-solving ability, and effective communication skills help interns collaborate with senior designers and accurately implement complex layouts. These skills and qualities are essential to ensure precise, manufacturable designs that meet performance and reliability standards in the semiconductor industry.

What are some common challenges faced by IC Layout Mask Designer interns, and how can they effectively overcome them?

As an IC Layout Mask Designer intern, you may encounter challenges such as learning specialized EDA (Electronic Design Automation) tools, understanding strict design rules, and interpreting complex circuit schematics. Collaborating closely with senior designers and asking clarifying questions can help you quickly get up to speed. Regularly reviewing layout guidelines, participating in team design reviews, and practicing with real-world design projects will also enhance your skills and confidence. Embracing feedback and staying organized are key to successfully managing the steep learning curve in this technical and detail-oriented role.
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Infographic showing various Internship Ic Layout Mask Designer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 7% Part Time, 1% Temporary, and 4% Contract. Highlights an 88% Physical, 6% Hybrid, and 6% Remote job distribution, with an average salary of $33,957 per year, or $16.3 per hour.
Analog/RF IC Layout Design Engineer

Analog/RF IC Layout Design Engineer

Keysight Technologies, Inc.

Santa Clara, CA

$117K - $195K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 28 days ago


Keysight Technologies rating

8.1

Company rating: 8.1 out of 10

Based on 20 frontline employees who took The Breakroom Quiz

43rd of 144 rated electronics manufacturers


Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.


Responsibilities

Keysight Technologies has been and will continue to be the world’s premier measurement company. Keysight Technologies has an opening for an Analog Layout Engineer in its ASIC/MMIC Design Center in Colorado Springs.

This specific position is to support a team of ASIC/MMIC designers by laying out full custom BiCMOS, CMOS, and bipolar (e.g., InP/GaAs) ICs for leading-edge test and

measurement products. Through close collaboration with IC designers and experts in IC technologies and IC design tools, you’ll help create breakthrough components for new Keysight products. The position also requires tools and CAD knowledge to develop methodologies and automation to increase productivity and effectiveness.

Job Aspects include:

  • Creating transistor level layout views from schematics, spanning from cell-level up through top-level and full-chip assembly
  • Completing Design Rule Checking (DRC), Layout-vs-Schematic (LVS), Antenna Checks, and maintaining Layout XL compliance
  • Placing device primitives using best practices for thermal and device matching, like common centroid, dummy matching, RF symmetry, interdigitation, etc.
  • Soliciting IC designers for advice and feedback on critical circuit nodes, matching requirements, current density requirements, and other critical parameters for circuit
  • success
  • Knowledge of electro-migration (EMIR) and how to best prevent and correct its effects
  • Understanding of metal density requirements and proper ways to address this type of DRC error
  • Assisting the design team with IC floorplanning, creating grid cells and other custom layouts
  • Coordinating layout activities with other layout engineers and contractors

Complete chip level sign-off verifications


Qualifications

Must have qualifications:

  • BS/MS in Electrical Engineering, or applicable degree and/or relevant experience
  • 7+ years of experience with custom Analog IC Layout experience
  • 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density/slot
  • rules
  • Familiarity with analog design in modern sub-micron BiCMOS (130 nm and smaller)
  • Knowledge of device matching, common centroid practices, parasitic effects, and other techniques for guaranteeing quality results
  • Ability to work on multiple cell designs in parallel in a dynamic environment
  • Experience with Version Control systems (e.g., SVN, Cliosoft/SOS)
  • Excellent teamwork, collaboration, and communication skills as you will work directly with IC design engineers and other layout designers

Additional skills that are nice to have:

  • Basic understanding of simple electrical circuits
  • Experience with Mentor Calibre DRC / LVS and similar EDA tools
  • Layout experience specifically for high-frequency (20+ GHz) bipolar signal path ICs
  • Linux fundamental knowledge
  • SKILL programming or other scripting experience
  • OCEAN experience

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

Careers Privacy Statement

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.

 

Most offers will be between the minimum and the midpoint of the Salary Range listed below.

MIN $117,530.00 - MAX $195,880.00

Note: For other locations, pay ranges will vary by region

This role is eligible for Keysight Results Bonus Program 

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)
  • Restricted Stock Units

#LI-MED1

Qualifications:

Must have qualifications:

  • BS/MS in Electrical Engineering, or applicable degree and/or relevant experience
  • 7+ years of experience with custom Analog IC Layout experience
  • 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density/slot
  • rules
  • Familiarity with analog design in modern sub-micron BiCMOS (130 nm and smaller)
  • Knowledge of device matching, common centroid practices, parasitic effects, and other techniques for guaranteeing quality results
  • Ability to work on multiple cell designs in parallel in a dynamic environment
  • Experience with Version Control systems (e.g., SVN, Cliosoft/SOS)
  • Excellent teamwork, collaboration, and communication skills as you will work directly with IC design engineers and other layout designers

Additional skills that are nice to have:

  • Basic understanding of simple electrical circuits
  • Experience with Mentor Calibre DRC / LVS and similar EDA tools
  • Layout experience specifically for high-frequency (20+ GHz) bipolar signal path ICs
  • Linux fundamental knowledge
  • SKILL programming or other scripting experience
  • OCEAN experience

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

Careers Privacy Statement

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.

 

Most offers will be between the minimum and the midpoint of the Salary Range listed below.

MIN $117,530.00 - MAX $195,880.00

Note: For other locations, pay ranges will vary by region

This role is eligible for Keysight Results Bonus Program 

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)
  • Restricted Stock Units

#LI-MED1

Education:UNAVAILABLEEmployment Type: UNAVAILABLE

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