Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $235K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $235K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Chip Lead / ASIC Director
San Jose, CA · On-site
$217K/yr
Master's or PhD in Electrical Engineering, Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Chip Lead / ASIC Director
San Jose, CA · On-site
$217K/yr
Master's or PhD in Electrical Engineering, Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Master's or PhD in Electrical Engineering,Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Master's or PhD in Electrical Engineering,Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity ...
We are hiring a Chip Firmware Validation Engineer to help us build the next generation of photonic ... Qualifications * BS in Electrical Engineering, Computer Science, or a related field with 5+ years ...
We are hiring a Chip Firmware Validation Engineer to help us build the next generation of photonic ... Qualifications * BS in Electrical Engineering, Computer Science, or a related field with 5+ years ...
Architect Labs is a frontier AI lab for chip design, focused on building AI models and tools for ... Qualifications : Required : • Education: BS/MS in Computer Science, Computer Engineering ...
Architect Labs is a frontier AI lab for chip design, focused on building AI models and tools for ... Qualifications : Required : • Education: BS/MS in Computer Science, Computer Engineering ...
Internship Computer Chip Engineer information
What is the difference between Internship Computer Chip Engineer vs Entry-Level Computer Chip Engineer?
| Aspect | Internship Computer Chip Engineer | Entry-Level Computer Chip Engineer |
|---|---|---|
| Qualifications | Currently enrolled or recent graduate, some coursework in electrical engineering or computer engineering | Bachelor's degree in electrical/computer engineering or related field |
| Work Environment | Internship programs, supervised tasks, learning-focused | Full-time professional role, project responsibilities |
| Employer & Industry | Tech companies, semiconductor firms, research labs | Semiconductor companies, tech firms, manufacturing |
Internship Computer Chip Engineers are students or recent graduates gaining hands-on experience, often part-time or temporary. Entry-Level Computer Chip Engineers are full-time professionals responsible for designing and testing chips. Internships serve as a stepping stone, while entry-level roles involve more responsibility and independence in the industry.
$2K/mo
Full-time
Medical, Dental, Vision
Posted 14 days ago
Job description
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Key responsibilities
- Own and manage Etched's front-end CAD environment including build flows, tool-specific flows and tool installation and configuration.
- Evaluate, deploy, and sustain front-end tools including but not limited to: RTL simulator, low power checker, static RTL checkers such as Lint, and CDC/RDC/SDC/DFT, and formal verification (both property and equivalence) checkers.
- Configure and manage project execution dashboard.
You may be a good fit if you have
- Experience developing and maintaining front-end IC design flows, including scripting and EDA tool configuration.
- Proficiency with (at least some) key verification tools: RTL simulation, static checks (lint/CDC/RDC), formal tools and low power tools.
- Ability to automate and optimize CAD workflows for chip design verification.
- Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in the relevant capabilities
- A can-do attitude and velocity of going from a problem sighting to a deployable solution.
- (Bonus) Hands-on RTL design experience, including ownership of a design block to validate CAD methodologies.
Strong candidates may also have experience
- Setting up and maintaining front-end IC design flows.
- Working directly with Synopsys and Cadence R&D, sales and field support teams.
- Working for other chip companies (i.e. Nvidia, Intel, AMD, Qualcomm, Marvell, Broadcom) or an internal chip team at a hyperscaler.
Benefits
- Full medical, dental, and vision packages, with 100% of premium covered
- Housing subsidy of $2,000/month for those living within walking distance of the office
- Daily lunch and dinner in our office
- Relocation support for those moving to Cupertino
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.