SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
Los Angeles, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Modeling/Drafting - Civil CAD Internship
San Diego, CA · On-site
$21/hr
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
Company Description At KPFF Consulting Engineers , we are more than just an engineering design firm ... AutoCAD Drafting Interns work in a close knit team environment in a rapidly expanding ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Experience in developing EDA tools for chip design flows including industry standard EDA tools ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
Experience in developing EDA tools for chip design flows including industry standard EDA tools ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface ... We do not have boundaries between engineering and research, and we expect all of our technical ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools ... Bachelor's degree in electrical engineering, computer engineering or computer science * 5+ years of ...
Chip Lead / ASIC Director
San Jose, CA · On-site
$217K/yr
Master's or PhD in Electrical Engineering, Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Chip Lead / ASIC Director
San Jose, CA · On-site
$217K/yr
Master's or PhD in Electrical Engineering, Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Master's or PhD in Electrical Engineering,Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Master's or PhD in Electrical Engineering,Computer Engineering, or related technical field * Post ... Chip Definition and Feasibility - identify critical tradeoffs and architectural decisions * Advise ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Chip Lead, Senior Director
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or related field * 15+ years of ...
Internship Computer Chip Engineer information
What is the difference between Internship Computer Chip Engineer vs Entry-Level Computer Chip Engineer?
| Aspect | Internship Computer Chip Engineer | Entry-Level Computer Chip Engineer |
|---|---|---|
| Qualifications | Currently enrolled or recent graduate, some coursework in electrical engineering or computer engineering | Bachelor's degree in electrical/computer engineering or related field |
| Work Environment | Internship programs, supervised tasks, learning-focused | Full-time professional role, project responsibilities |
| Employer & Industry | Tech companies, semiconductor firms, research labs | Semiconductor companies, tech firms, manufacturing |
Internship Computer Chip Engineers are students or recent graduates gaining hands-on experience, often part-time or temporary. Entry-Level Computer Chip Engineers are full-time professionals responsible for designing and testing chips. Internships serve as a stepping stone, while entry-level roles involve more responsibility and independence in the industry.
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$165K - $260K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 6 days ago
SpaceX rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
14th of 60 rated aerospace companies
Job description
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
- Develop, maintain, and optimize physical verification flows for advanced node SoC's.
- Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
- Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
- Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
- Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
- Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
- Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
- Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
- Deep expertise in DRC, LVS, PERC and ESD verification methodologies
- Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
- Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
- Experience at advanced nodes (4nm and below)
- Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
- Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
About SpaceX
Sourced by ZipRecruiter
Industry
Accounting services
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US
Year founded
2002