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Internship Cadence Design Jobs (NOW HIRING)

Vantiva

Hardware Design & Test Engineer

Carmel, IN · On-site

Internship or project experience in hardware design or testing. * Knowledge of PCB design tools (e.g., Cadence, OrCAD). * Basic scripting or programming skills (e.g., Python, MATLAB) Our most ...

Vantiva

Hardware Design & Test Engineer

Carmel, IN

Internship or project experience in hardware design or testing. * Knowledge of PCB design tools (e.g., Cadence, OrCAD). * Basic scripting or programming skills (e.g., Python, MATLAB) Our most ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

... and Cadence (e.g., Innovus, Virtuoso, SimVision). * Proficiency in scripting languages such as ... Prior internship or professional experience in physical design, circuit design, or related ...

Intel

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

... and Cadence (e.g., Innovus, Virtuoso, SimVision). * Proficiency in scripting languages such as ... Prior internship or professional experience in physical design, circuit design, or related ...

Intel Corporation

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design ...

Intel

Physical Design Methodology Engineer

Phoenix, AZ · On-site

$164K - $269K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Experience in working with BOTH Cadence and Synopsys EDA tool/flow * Demonstrated ability to work ...

Intel

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design ...

Intel

Physical Design Methodology Engineer

Austin, TX · On-site

$164K - $269K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Experience in working with BOTH Cadence and Synopsys EDA tool/flow * Demonstrated ability to work ...

Intel Corporation

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design ...

Intel Corporation

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications ... Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design ...

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Internship Cadence Design information

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How much do internship cadence design jobs pay per hour?

As of Jul 13, 2026, the average hourly pay for internship cadence design in the United States is $16.33, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship Cadence Design, and why are they important?

To excel in a Cadence Design internship, you generally need a background in electrical engineering or computer science, along with a solid understanding of digital or analog circuit design concepts. Familiarity with Cadence EDA tools (such as Virtuoso, Allegro, or OrCAD), scripting languages, and simulation software is highly valuable. Strong analytical thinking, problem-solving skills, and effective teamwork set exceptional interns apart. These skills and qualifications enable interns to contribute meaningfully to design projects and adapt quickly to industry-standard workflows.

What is an Internship at Cadence Design?

An Internship at Cadence Design is a temporary, supervised work experience offered to students or recent graduates interested in the electronic design automation (EDA) industry. Interns at Cadence have the opportunity to work alongside experienced engineers and professionals, contributing to real-world projects in areas such as semiconductor design, software development, and verification. The program is designed to provide hands-on learning, professional development, and exposure to cutting-edge technology, often leading to potential full-time employment opportunities after graduation.

What are some typical projects or tasks that an intern at Cadence Design can expect to work on?

As an intern at Cadence Design, you can expect to engage in hands-on projects that support the development and testing of electronic design automation (EDA) tools. Typical tasks may include collaborating with experienced engineers to write and debug code, assist in the simulation and verification of integrated circuits, and contribute to documentation or user support efforts. You’ll often work within cross-functional teams, gaining exposure to both software and hardware design processes. This experience helps interns build practical skills and establish connections for future career opportunities within the semiconductor industry.
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Internship Cadence Design jobs near you
Infographic showing various Internship Cadence Design job openings in the United States as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $33,957 per year, or $16.3 per hour.
Founding Hardware Engineer

Founding Hardware Engineer

Brahma Consulting Group

San Francisco, CA • On-site

Full-time

Re-posted 9 days ago

Job description

We’re looking for hardware engineers with hands-on experience in chip design workflows—ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading EDA vendors such as Synopsys or Cadence. Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML workflows will stand out.


Responsibilities

  • Drive direction and technical leadership across our multi-agent platform and domain-specific hardware knowledge base.
  • Bring a deep understanding of chip design workflows and help shape product roadmap with real-world context.
  • Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages.
  • Track evolving trends in both semiconductor design and AI-assisted design automation.
  • Create internal benchmarks and datasets to rigorously evaluate system performance across RTL, PD, and architectural use cases.


Qualifications

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline (interns may be considered for their flair).
  • Hands-on experience in a semiconductor or EDA environment (e.g., NVIDIA, AMD, Intel, Synopsys, Cadence), 1+ years of full-time experience required, 3+ years preferred.
  • Proficiency in scripting (Python, Bash) and experience with automation or tooling for design verification or integration.


SPECIALTY: DI (Design Integration, RTL, Architecture)

  • Proven track record of developing architectures and RTL for hardware blocks or IP.
  • Experience with SystemVerilog, Verilog & SoC design methodologies.


SPECIALTY: PD (Physical Design)

  • Part of leading edge tapeouts (7nm or smaller). Worked on at least one of synthesis, floor planning, place-and-route, physical verification, and timing.
  • Familiar with one of Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler, or other relevant EDA CAD tool (and associated TCL).


Preferred Experience

  • Experience on AI-for-chip-design initiatives (e.g., at Synopsys, NVIDIA, GoogleDeepMind).
  • Understanding of DFT, power optimization techniques, or low-power design flows.
  • Experience on an IP development team, developing PCIe, PHY, LPDOR, MemoryControllers, NoC, CPU subsystems, or similar.