RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
PE Logic Design
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
PE Logic Design
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... internship experience. Benefits at Intel Our total rewards package goes above and beyond just a ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... internship experience. Benefits at Intel Our total rewards package goes above and beyond just a ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Senior ASIC Emulation Engineer
OR · On-site +1
$170K - $250K/yr
You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...
Senior ASIC Emulation Engineer
OR · On-site +1
$170K - $250K/yr
You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
PE Logic Design
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
PE Logic Design
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
PE Logic Design
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
PE Logic Design
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ... Your successful track record of mentoring junior engineers and interns a huge plus. A strong ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ... Your successful track record of mentoring junior engineers and interns a huge plus. A strong ...
Internship Asic Rtl Design Engineer information
What is an internship ASIC RTL design engineer?
An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.
What does an internship ASIC RTL design engineer do?
As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.
What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?
To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Oregon?
The most popular types of Asic Rtl Design Engineer jobs in Oregon are:
What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Oregon?
For Internship Asic Rtl Design Engineer jobs in Oregon, the most frequently searched job titles are:
- Mechanical Design
- Junior Mechanical Design Engineer
- Contract Design Engineer
- Freelance Mechanical Design Engineer
- Work From Home Design Verification Engineer
- Remote Motorcycle Design Engineer
- Mechanical Design Engineer
- Work From Home Gearbox Design Engineer
- Entry Level Mechanical Design Engineer
- Senior Design Engineer
What job categories do people searching Internship Asic Rtl Design Engineer jobs in Oregon look for?
The top searched job categories for Internship Asic Rtl Design Engineer jobs in Oregon are:
What cities in Oregon are hiring for Internship Asic Rtl Design Engineer jobs?
Cities in Oregon with the most Internship Asic Rtl Design Engineer job openings:
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team!
This role will build upon your solid foundation in digital logic circuits while introducing mixed-signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits, ensuring formal equivalence between custom designs and their abstract representations. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities.
Description
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
Synthesis, static timing analysis, and design-for-test (DFT)
SystemVerilog assertions, checkers, and advanced verification techniques
Scripting languages (Perl, Python)
Formal verification and low-power design methodologies
Hardware-software co-design and system-level optimization
Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design
This role will build upon your solid foundation in digital logic circuits while introducing mixed-signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits, ensuring formal equivalence between custom designs and their abstract representations. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities.
Description
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
Synthesis, static timing analysis, and design-for-test (DFT)
SystemVerilog assertions, checkers, and advanced verification techniques
Scripting languages (Perl, Python)
Formal verification and low-power design methodologies
Hardware-software co-design and system-level optimization
Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976