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Internship Asic Rtl Design Engineer Jobs in Oregon

Intel

Senior CPU RTL Design Engineer

Hillsboro, OR · On-site

  • Medical

  • Retirement

  • PTO

As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... internship experience. Benefits at Intel Our total rewards package goes above and beyond just a ...

Intel

Senior CPU RTL Design Engineer

Hillsboro, OR · On-site

  • Medical

  • Retirement

  • PTO

As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... internship experience. Benefits at Intel Our total rewards package goes above and beyond just a ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Apple

ASIC Design Engineer

Beaverton, OR · On-site

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127.40 - $236.60/hr

  • Medical

  • Dental

  • Retirement

Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR · On-site

$172K/yr

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR · On-site

$172K/yr

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Apple Inc.

ASIC Design Engineer

Beaverton, OR · On-site

$150 - $210/hr

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

Apple

DDR Design Engineer

Beaverton, OR

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

DDR Design Engineer

Beaverton, OR · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

  • Medical

  • Dental

  • Retirement

RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

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Internship Asic Rtl Design Engineer information

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Infographic showing various Internship Asic Rtl Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 50% Full Time, 13% Part Time, and 37% Contract. Highlights an 100% In-person job distribution.

Senior CPU RTL Design Engineer

Intel

Hillsboro, OR • On-site

Full-time

Medical, Retirement, PTO

Re-posted 14 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:Job Description: 
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

Life at Intel


We developed the Intel microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who is hands-on with RTL implementation for integer, floating point and reservation station logic and can provide technical leadership to deliver world-class products.
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to:
Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Technical Guidance: Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.
Cross team collaboration: Work closely with architecture and backend teams and with other design teams towards achieving best-in-class products.
Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.
Behavioral traits that we are looking for:
Excellent in problem-solving, analytical.
Excellent written and verbal communication skills.
Ability to work effectively in a fast-paced environment and collaborative environment.
Qualifications:
Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Minimum Qualifications:


Education Requirement
Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 8+ years of work experience OR
Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 7+ years of work experience OR
PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 4+ years of work experience.
Minimum Required Qualifications:
6+ years of experience in silicon development in CPU microarchitecture and logic design.
5+ years of experience in technical leadership including delivering successful IP Projects.
6+ years of experience with Timing Closure, Power Convergence;integer and/or floating point, OOO execution, reservation station design.
Additional Preferred Qualifications:


Advanced degree in Computer Science, Electrical, Electronics, Engineering, or related field.

Experience on x86 CPU microarchitecture
Experience with driving front end methodologies and championing the use of automation / AI tools to realize tangible benefits visible at the product level.
Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits ' Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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Benefits

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Workplace

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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