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Ic Packaging Jobs (NOW HIRING)

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating ...

One of our valued Client is looking for the below requirement IC Packaging Design Engineer LOC: Chandler, AZ or Hillsboro, OR Longterm Contract Skills Required Bachelor's or Master's degree in ...

We are looking for a hardworking, and passionate IC Packaging Engineering Lead to join our team. Description • Work with cross-functional teams and lead package integration and architecture efforts ...

We are looking for a hardworking, and passionate IC Packaging Engineering Lead to join our team. Description • Work with cross-functional teams and lead package integration and architecture efforts ...

We are looking for a hardworking and passionate IC Packaging Assembly Engineer to join our team. In this highly visible role, you will own development, optimization and sustaining the advanced flip ...

Senior Photonics Packaging Engineer

Bozeman, MT · On-site

$106K - $146K/yr

As a Senior Photonics Engineer specializing in Photonic IC Packaging, you are a technical leader responsible for designing, developing, and scaling advanced photonic packaging solutions. You drive ...

We are looking for a hardworking and passionate IC Packaging Assembly Engineer to join our team. In this highly visible role, you will own development, optimization and sustaining the advanced flip ...

Packaging Engineer

San Jose, CA · On-site

$86K - $118K/yr

IC package design: design and optimize IC packages for a wide range of ADI products, using common and advanced analog IC package platforms and assembly/bumping processes. * Power module and system ...

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

Packaging Engineer

San Jose, CA · On-site

$86K - $118K/yr

IC package design: design and optimize IC packages for a wide range of ADI products, using common and advanced analog IC package platforms and assembly/bumping processes. * Power module and system ...

Package Integration Engineer

San Francisco, CA · On-site

$122K - $164K/yr

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

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Ic Packaging information

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How much do ic packaging jobs pay per hour?

As of Jun 28, 2026, the average hourly pay for ic packaging in the United States is $18.85, according to ZipRecruiter salary data. Most workers in this role earn between $16.35 and $19.95 per hour, depending on experience, location, and employer.

Is IC a serious condition?

In the context of IC Packaging, the term 'IC' refers to integrated circuits, which are electronic components used in manufacturing. IC packaging involves protecting and connecting these circuits, and it is not related to any medical condition. Therefore, 'IC' in this job role is not a serious condition but a technical term in electronics manufacturing.

What are some common challenges faced by professionals working in IC packaging, and how can job seekers prepare for them?

Professionals in IC packaging often encounter challenges such as keeping up with rapid advancements in packaging technologies, ensuring high yield and reliability, and managing cross-functional communication between design, manufacturing, and testing teams. Job seekers can prepare by staying current with industry trends, developing strong problem-solving skills, and gaining hands-on experience with various packaging methods. Additionally, effective collaboration and a willingness to learn from both successes and setbacks are essential for long-term success in this dynamic field.

What are the key skills and qualifications needed to thrive as an IC Packaging Engineer, and why are they important?

To thrive as an IC Packaging Engineer, you typically need a background in electrical, mechanical, or materials engineering and knowledge of semiconductor packaging principles. Familiarity with design tools such as AutoCAD, ANSYS, and semiconductor process simulation software, along with relevant certifications like IPC standards, is crucial. Strong problem-solving, attention to detail, and effective teamwork skills help drive innovation and ensure high-quality outcomes. These competencies are vital for developing reliable, efficient integrated circuit packages that meet industry standards and customer requirements.

Does ibuprofen help interstitial cystitis?

As an IC packaging professional, it is important to understand that ibuprofen is a nonsteroidal anti-inflammatory drug (NSAID) used to reduce pain and inflammation. However, its effectiveness for interstitial cystitis (IC) varies, and it is not a primary treatment for IC. Patients should consult healthcare providers for appropriate management options for IC symptoms.

What is the difference between Ic Packaging vs IC Design Engineer?

AspectIC PackagingIC Design Engineer
Required CredentialsTypically requires a degree in electrical engineering, materials science, or related fields; certifications in packaging technologies are a plus.Requires a degree in electrical engineering, computer engineering, or related fields; often includes certifications in digital or analog design.
Work EnvironmentManufacturing facilities, R&D labs, and cleanrooms focused on physical packaging and assembly.Design labs, CAD environments, and simulation tools for circuit design and testing.
Employer & Industry UsageFound in semiconductor companies, electronics manufacturers, and R&D centers.Employed by semiconductor firms, integrated circuit companies, and design houses.

IC Packaging and IC Design Engineer roles are closely related but focus on different stages of semiconductor development. IC Packaging involves physically enclosing and protecting the chip, requiring expertise in materials and manufacturing processes. IC Design Engineers focus on creating the circuit layouts and functionalities of the chips. Both roles are essential in the semiconductor industry and often collaborate during product development.

What is IC packaging?

IC packaging refers to the process of enclosing integrated circuits (ICs) in a protective case that allows for electrical connection and heat dissipation. The package safeguards the delicate silicon chip from physical damage and environmental factors while enabling it to be mounted onto printed circuit boards (PCBs). IC packaging types vary in complexity and size, including options like DIP, QFP, BGA, and more, each suited for different applications and performance needs. The packaging also plays a critical role in determining the device's electrical performance, thermal management, and overall reliability.

What is IC short for?

In the context of IC Packaging, IC stands for Integrated Circuit, which is a set of electronic circuits manufactured on a small semiconductor chip. IC Packaging involves enclosing the chip in a protective case with electrical connections, requiring knowledge of semiconductor devices and manufacturing processes.

Is IC an autoimmune disease?

IC Packaging is a manufacturing process for integrated circuits and is not related to autoimmune diseases. It involves assembling semiconductor components into protective packages, requiring skills in electronics and cleanroom environments. This job does not involve medical or health-related diagnoses or treatments.
More about Ic Packaging jobs
What cities are hiring for Ic Packaging jobs? Cities with the most Ic Packaging job openings:
What states have the most Ic Packaging jobs? States with the most job openings for Ic Packaging jobs include:
Infographic showing various Ic Packaging job openings in the United States as of June 2026, with employment types broken down into 97% Full Time, 1% Part Time, and 2% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $39,198 per year, or $18.8 per hour.

IC Package Engineer

Etched

Cupertino, CA

$2.0K/mo

Full-time

Medical, Dental, Vision

Posted 4 days ago


Job description

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

IC Package Engineer

We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.

Representative Projects:

  • Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions
  • Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed
  • Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design
  • Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress
  • Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities
  • Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams to ensure holistic package solutions, while interfacing with vendors to align design requirements and production feasibility
  • Oversee package reliability testing, including thermal, warpage, shock, shear, HTSL, HAST, ALT, JESD22, and electrical tests, while interfacing with various vendors to ensure compliance and quality

You maybe a good fit if you have

  • Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, or related discipline
  • 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies
  • Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W
  • Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes
  • Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar
  • Familiarity with mechanical stress analysis, simulation, and validation methodologies
  • Solid communication skills to work across multi-disciplinary teams and external partners
  • Experience with advanced packaging nodes (e.g., 2.5D/3D stacking)
  • Knowledge of thermal management techniques in package design
  • Previous experience working in AI, HPC, or semiconductor design companies

We encourage you to apply even if you do not believe you meet every single qualification.

How we're different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits:

  • Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino