... IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization Concepts of timing closure and related industry tools (e.g ...
... IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization Concepts of timing closure and related industry tools (e.g ...
Senior Hardware Design Engineer (Teradyne, Tualatin, OR)
Tualatin, OR · On-site
$141K - $226K/yr
Here, we design IC testers for the DRAM and FLASH memory market. Opportunity Overview As a Hardware ... Relevant PCB layout experience to guide CAD personnel * Experience with circuit simulation tools (e ...
Senior Hardware Design Engineer (Teradyne, Tualatin, OR)
Tualatin, OR · On-site
$141K - $226K/yr
Here, we design IC testers for the DRAM and FLASH memory market. Opportunity Overview As a Hardware ... Relevant PCB layout experience to guide CAD personnel * Experience with circuit simulation tools (e ...
Senior Hardware Design Engineer (Teradyne, Tualatin, OR)
Tualatin, OR · On-site
$141K - $226K/yr
Here, we design IC testers for the DRAM and FLASH memory market. Opportunity Overview As a Hardware ... Relevant PCB layout experience to guide CAD personnel * Experience with circuit simulation tools (e ...
Senior Hardware Design Engineer (Teradyne, Tualatin, OR)
Tualatin, OR · On-site
$141K - $226K/yr
Here, we design IC testers for the DRAM and FLASH memory market. Opportunity Overview As a Hardware ... Relevant PCB layout experience to guide CAD personnel * Experience with circuit simulation tools (e ...
... IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization Concepts of timing closure and related industry tools (e.g ...
... IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization Concepts of timing closure and related industry tools (e.g ...
OR · On-site
$145K - $160K/yr
... into a lead or senior IC role. * Portfolio showing end-to-end ownership of complex B2B or ... Deep proficiency in Figma, including component libraries, auto-layout, and prototyping. * Hands-on ...
OR · On-site
$145K - $160K/yr
... into a lead or senior IC role. * Portfolio showing end-to-end ownership of complex B2B or ... Deep proficiency in Figma, including component libraries, auto-layout, and prototyping. * Hands-on ...
Ic Layout information
See Oregon salary details
$16.64 is the 25th percentile. Wages below this are outliers.
$11.69 - $17.14
28% of jobs
The median wage is $20 / hr.
$17.14 - $22.60
43% of jobs
$23.66 is the 75th percentile. Wages above this are outliers.
$22.60 - $28.05
23% of jobs
$28.05 - $33.50
6% of jobs
$33.50 - $38.96
0% of jobs
$38.96 - $44.41
0% of jobs
$44.41 - $49.86
0% of jobs
$49.86 - $55.31
0% of jobs
$55.31 - $60.77
0% of jobs
$60.77 - $66.22
0% of jobs
$66.22 - $71.67
0% of jobs
$11
$23
$71
How much do ic layout jobs pay per hour?
What are the key skills and qualifications needed to thrive in the IC layout position, and why are they important?
To thrive as an IC Layout professional, you need strong proficiency in analog and digital integrated circuit (IC) layout design, a solid understanding of semiconductor physics, and a degree in electrical engineering or a related field. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required. Attention to detail, effective communication, and the ability to collaborate with circuit design engineers are valuable soft skills. These qualities ensure that layouts are precise, manufacturable, and meet stringent performance and reliability standards in the semiconductor industry.
What are some common challenges faced by IC layout engineers, and how do they typically overcome them?
IC Layout engineers often encounter challenges such as balancing area constraints with performance requirements, minimizing parasitic effects, and ensuring adherence to complex design rules. These challenges are addressed by leveraging advanced EDA tools, closely collaborating with circuit designers to understand specific needs, and frequently reviewing and updating the layout to align with fabrication requirements. Strong analytical thinking and attention to detail are essential for identifying and solving these issues. By keeping up with evolving technology and continually honing their skills, IC Layout engineers can efficiently deliver robust and high-quality designs.
What is an IC layout?
An IC Layout job involves designing the physical layout of integrated circuits (ICs) to ensure they meet electrical, manufacturing, and performance requirements. Layout engineers use specialized software to place and route transistors, resistors, and metal interconnects while following design rules and constraints. They work closely with circuit designers to optimize the layout for power, performance, and area. The role requires knowledge of semiconductor manufacturing processes and layout verification techniques such as DRC (Design Rule Checking) and LVS (Layout vs. Schematic).

Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create, execute and drivestate-of-the-art IPs key to Apple’s products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.
If you have strong fundamentals and a track record of tackling technical challenges,
If you are passionate about learning new skills and improving the value of your work,
If you like to be tuned to the big picture while diving deeply into the details to innovate and tackle problems.
We invite you to join and grow with our team!
Description
You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA).
You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
Preferred Qualifications
Deep understanding of analog mixed-signal design with experience in high-speed serial links.
Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
Understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
Proven track record of working with system and architecture teams to drive block-level and IP requirements for high-speed IO in 100+ Gbps NRZ and PAM applications
Proven track record of working with large teams and guiding junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO.
Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 100+ Gbps NRZ and PAM applications
Experience with EQ adaptation methods and circuit implementations to improve PPA
Solid understanding of CDR architectures and implementations
Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
Hands-on experience to drive lab testing, debug and data analysis
Hands-on experience in advanced CMOS technologies, design with FinFet technology
Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
Concepts of IP delivery and quality checks
Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired
Skills in scripting and automation to enhance efficiency are highly desirable
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976