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Full Time Semiconductor Design Jobs (NOW HIRING)

Amat

Design Engineer

Santa Clara, CA

$156K - $214K/yr

... full-time team member. The successful candidate will provide technical support and operational ... This role requires a strong understanding of semiconductor design infrastructure, EDA workflows ...

New

Applied Materials

Design Engineer

Santa Clara, CA · On-site

$156K - $214K/yr

... full-time team member. The successful candidate will provide technical support and operational ... This role requires a strong understanding of semiconductor design infrastructure, EDA workflows ...

New

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills: * Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or distributed compute ...

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills: * Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or distributed compute ...

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills: * Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or distributed compute ...

Micron

Staff Engineer, CE CAD

Richardson, TX · On-site

$106K - $267K/yr

The AI Design Enablement team focuses on applying AI-assisted methods to real semiconductor design ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...

Micron

Staff Engineer, CE CAD

San Jose, CA · On-site

$106K - $267K/yr

The AI Design Enablement team focuses on applying AI-assisted methods to real semiconductor design ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...

Micron

Staff Engineer, CE CAD

Boise, ID · On-site

$106K - $267K/yr

The AI Design Enablement team focuses on applying AI-assisted methods to real semiconductor design ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...

Micron Technology

Staff Engineer, CE CAD

Richardson, TX · On-site

$106K - $267K/yr

The AI Design Enablement team focuses on applying AI-assisted methods to real semiconductor design ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA

... , full-time , onsite roles in Silicon Valley supporting advanced semiconductor and AI / networking programs. These roles are within a leading semiconductor design services organization, supporting ...

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Full Time Semiconductor Design information

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How much do full time semiconductor design jobs pay per hour?

As of Jul 29, 2026, the average hourly pay for full time semiconductor design in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.
What are the most commonly searched types of Semiconductor Design jobs? The most popular types of Semiconductor Design jobs are:
Full Time Semiconductor Design jobs near you

Dir, CAD Eng R&D

Lattice Semiconductor

San Jose, CA • On-site

Full-time

Re-posted 19 days ago

Job description

Lattice OverviewThere is energy here...energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.Responsibilities & Skills

Description: Director - CAD Design Engineering & EDA Infrastructure

Role Overview

The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting-edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality.

Key Responsibilities
  • EDA Strategy: Define and drive the long-term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design.
  • Methodology Development: Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign-off.
  • Infrastructure Management: Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency.
  • GenAI Strategy for the EDA Design and Methodology
  • Cross-functional Collaboration: Partner with design, verification, CAD, and IT teams to align methodologies with project needs.
  • Tool Evaluation: Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance.
  • Innovation Leadership: Introduce automation, AI/ML-driven flows, and cloud-native solutions to accelerate design productivity.
  • Team Leadership: Build and mentor a high-performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation.
  • Process Standardization: Establish best practices, documentation, and training programs for design teams worldwide.
  • Risk Management: Identify and mitigate risks in tool flows, infrastructure, and project schedules.

Qualifications

  • Education: Master's in electrical engineering, Computer Engineering, or related field.
  • Experience: 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership.
  • Technical Expertise: Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off flows.
  • Infrastructure Knowledge: Strong background in compute infrastructure, cloud-based design environments, and license management.
  • Leadership Skills: Proven ability to lead global teams, manage vendor relationships, and drive organizational change.
  • Soft Skills: Excellent communication, negotiation, and strategic planning abilities.
Impact

This role is pivotal in enabling the company to design next-generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time-to-market, and maintain design quality at scale.

Employment Type: FULL_TIME

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