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Full Time Semiconductor Design Jobs (NOW HIRING)

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

... , full-time , onsite roles in Silicon Valley supporting advanced semiconductor and AI / networking programs. These roles are within a leading semiconductor design services organization, supporting ...

Mirafra Technology

Test Automation Engineer

San Diego, CA

$48.75 - $64.50/hr

... semiconductor design, embedded and application software. Title : Test Automation Engineer Type : Full Time with Mirafra Inc (deputed to the client Qualcomm) Location : San Diego, CA SW engineer ...

Siemens

$18 - $50/hr

Potential for full-time offers after university graduation and completion of the program ... Semiconductor and IC design methodologies * Analog and digital electronics * 3D-IC and advanced ...

Siemens

$18 - $50/hr

Potential for full-time offers after university graduation and completion of the program ... Semiconductor and IC design methodologies * Analog and digital electronics * 3D-IC and advanced ...

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How much do full time semiconductor design jobs pay per hour?

As of Sep 9, 2026, the average hourly pay for full time semiconductor design in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.

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Full Time Semiconductor Design jobs near you

Founding Hardware Engineer

San Francisco, CA • On-site

Brahma Consulting Group
Recruiting and Staffing Services • 11 - 50 employees
Learn more about Brahma Consulting Groupexternal

Full-time

Re-posted 7 days ago

Job description

We’re looking for hardware engineers with hands-on experience in chip design workflows—ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading EDA vendors such as Synopsys or Cadence. Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML workflows will stand out.


Responsibilities

  • Drive direction and technical leadership across our multi-agent platform and domain-specific hardware knowledge base.
  • Bring a deep understanding of chip design workflows and help shape product roadmap with real-world context.
  • Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages.
  • Track evolving trends in both semiconductor design and AI-assisted design automation.
  • Create internal benchmarks and datasets to rigorously evaluate system performance across RTL, PD, and architectural use cases.


Qualifications

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline (interns may be considered for their flair).
  • Hands-on experience in a semiconductor or EDA environment (e.g., NVIDIA, AMD, Intel, Synopsys, Cadence), 1+ years of full-time experience required, 3+ years preferred.
  • Proficiency in scripting (Python, Bash) and experience with automation or tooling for design verification or integration.


SPECIALTY: DI (Design Integration, RTL, Architecture)

  • Proven track record of developing architectures and RTL for hardware blocks or IP.
  • Experience with SystemVerilog, Verilog & SoC design methodologies.


SPECIALTY: PD (Physical Design)

  • Part of leading edge tapeouts (7nm or smaller). Worked on at least one of synthesis, floor planning, place-and-route, physical verification, and timing.
  • Familiar with one of Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler, or other relevant EDA CAD tool (and associated TCL).


Preferred Experience

  • Experience on AI-for-chip-design initiatives (e.g., at Synopsys, NVIDIA, GoogleDeepMind).
  • Understanding of DFT, power optimization techniques, or low-power design flows.
  • Experience on an IP development team, developing PCIe, PHY, LPDOR, MemoryControllers, NoC, CPU subsystems, or similar.