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Full Time Pdk Engineer Jobs (NOW HIRING)

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Standard Cell Design Lead

San Francisco, CA · On-site

$150K - $275K/yr

We are a team of world-class scientists, engineers, and technical experts building technology for ... This is a full-time, onsite position. Responsibilities * Lead standard cell library development ...

Draper

ASIC CAD Engineer

Cambridge, MA · On-site

$82K - $220K/yr

They enable the use of EDA tools, maintain EDA licenses, install PDK data, support the compute farm ... Massachusetts Job Location - Postal Code: 02139-3563 The US base salary range for this full-time ...

Draper

ASIC CAD Engineer

Cambridge, MA · On-site

$82K - $220K/yr

They enable the use of EDA tools, maintain EDA licenses, install PDK data, support the compute farm ... Massachusetts Job Location - Postal Code: 02139-3563 The US base salary range for this full-time ...

E-Space

Senior Physical Design Engineer

Saratoga, CA · On-site

$120K - $220K/yr

... PDK constraints • Strong problem-solving skills and attention to detail in a deadline-driven ... This is a full time, exempt position, based out of our Saratoga office. The target base pay for ...

E-Space

Senior Physical Design Engineer

Saratoga, CA · On-site

$120K - $220K/yr

... PDK constraints Strong problem-solving skills and attention to detail in a deadline-driven ... This is a full time, exempt position, based out of our Saratoga office. The target base pay for ...

Qorvo, Inc.

IC Layout Engineering Intern

Richardson, TX · On-site

$31 - $42/hr

Final presentation to business leaders Qorvo's IC Layout Engineer Internships are offered in our ... Learn and apply foundry PDK design rules and layout methodologies. * Support block level floor ...

Wyetech

Hardware/Software Design Engineer 3

Annapolis, MD · On-site

$73.94 - $100.13/hr

Additional experience with Vivado required; experience with Epiq Solution PDK preferred The ... Full-time employees have the option to participate in a variety of voluntary benefit plans ...

Qorvo, Inc.

IC Layout Engineering Intern

Richardson, TX · On-site

$31 - $42/hr

Final presentation to business leaders Qorvo's IC Layout Engineer Internships are offered in our ... Learn and apply foundry PDK design rules and layout methodologies. * Support block level floor ...

Secure Site Solutions, Inc.

$42/hr

Orange County / Los Angeles, CA Position Type: Full-Time Compensation and Benefits * Pay: $36.00 ... This position involves the installation, programming, commissioning, and maintenance of Access ...

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Full Time Pdk Engineer information

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$36.5K

$107.3K

$137.5K

How much do full time pdk engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for full time pdk engineer in the United States is $107,282.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,500.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Full Time Pdk Engineer vs Full Time ASIC Design Engineer?

AspectFull Time Pdk EngineerFull Time ASIC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; familiarity with PDKsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; strong digital design background
Work EnvironmentDesign houses, foundries, semiconductor companiesSemiconductor companies, design firms, integrated device manufacturers
Industry UsageUsed primarily in process design kit development and customizationUsed in designing and verifying integrated circuits and chips

While both roles require a background in VLSI and semiconductor processes, a Full Time Pdk Engineer focuses on developing and maintaining process design kits, whereas a Full Time ASIC Design Engineer concentrates on designing and verifying application-specific integrated circuits. The roles often overlap in industry but serve different stages of chip development.

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Full Time Pdk Engineer jobs near you
Infographic showing various Full Time Pdk Engineer job openings in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 90% In-person, 5% Hybrid, and 5% Remote job distribution, with an average salary of $107,282 per year, or $51.6 per hour.

Staff Silicon Photonics Design Engineer

Neurophos Inc

Sunnyvale, CA • On-site

$230K - $280K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 4 days ago

Key responsibilities

  • Design, simulate, and optimize passive silicon photonic components such as edge couplers, grating couplers, and hybrid/directional couplers.

  • Develop waveguide routing, splitters, polarization splitters/rotators, crossings, and other PIC sub-elements with attention to performance metrics and process variation.

  • Manage and drive tapeout processes with foundries and interface with process engineers to resolve integration challenges.

Job description

About Neurophos
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We've assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft's Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Position Overview
We are seeking an experienced Silicon Photonics Designer to join our SiPh team. In this role, you will own the end-to-end design, simulation, layout, and characterization of passive silicon photonic components-including edge couplers, grating couplers, and hybrid/directional couplers-targeting a high-performance co-packaged optics system for artificial intelligence Inference applications. You will work directly with renowned foundry partners and cross-functional teams in VLSI, packaging, systems, and testing to bring photonic designs from concept to production-ready silicon.
Location
Austin, TX or Sunnyvale, CA. Full-time onsite position.
Key Responsibilities
  • Design, simulate, and optimize passive silicon photonic building blocks: edge couplers (inverse tapers, spot-size converters), grating couplers (1D/2D, chirped/apodized, dual-polarization), and hybrid/directional/multimode-interference (MMI) couplers for compact PIC designs.
  • Develop waveguide routing, splitters, polarization splitters/rotators (PSR), crossings, and other PIC sub-elements with explicit attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
  • Conduct FDTD, eigenmode expansion (EME), and circuit-level simulations using Ansys Lumerical, Synopsys Optsim, or equivalent tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
  • Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow, generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
  • Manage and drive tapeout processes with mainstream SiPh foundries, or equivalent silicon photonics PDKs
  • Interface directly with foundry process engineers to negotiate design rule waivers, understand process corners, and resolve integration challenges throughout the design cycle.
  • Define and execute design-of-experiments (DOE) test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.

Qualifications
  • M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
  • 3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record).
  • Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms.
  • Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation.
  • Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation.
  • Familiarity with electro-optic device design (Lasers, MZM, ring modulator, Ge photodetector) to enable holistic PIC integration.
  • Experience with at least one commercial silicon photonics foundry PDK and tapeout flow (TSMC, GlobalFoundries - GF Fotonix /AMF, Tower, AIM Photonics, or equivalent).
  • Programming proficiency in Python and/or MATLAB for simulation automation, data analysis, and statistical evaluation of device performance.
  • Working knowledge of datacom or coherent transceiver link architectures and system-level optical specifications.
  • Experience with coherent PIC design elements: IQ modulators, optical hybrids (90° hybrid), polarization splitters/rotators, and balanced detector integration.

Preferred Skills
  • Direct foundry interface experience with silicon photonics platforms-including DRC/LVS sign-off, OPC coordination, and MPW/dedicated wafer shuttle management.
  • Full tape-out ownership: concept → simulation → layout → DRC clean → tapeout → wafer receipt → measurement → design iteration.
  • Strong knowledge on high-speed optoelectronics device design and measurement
  • Hands-on optical measurement skills: coupling loss/insertion loss characterization, swept-wavelength spectral measurements, polarization-dependent loss (PDL) measurements.
  • Familiarity with SiN photonics platforms (low-loss, broadband) for edge coupler or wavelength-routing applications.
  • Good knowledge on wafer backend process and optical packaging: lensed-fiber or FAU edge-coupling assembly, active alignment, and fiber attachment processes for photonic modules.
  • Exposure to co-packaged optics (CPO) architectures, flip-chip or die bonding of III-V laser sources, or heterogeneous photonic integration.
  • Experience with automated measurement scripting (Python GPIB/VISA frameworks, automated wafer-level or die-level test stations).
  • Publications, patents, or conference presentations (OFC, ECOC, SPIE Photonics West) demonstrating silicon photonics design contributions.

What We Offer
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You'll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Benefits
Join a team that invests in your future and your well-being. At Neurophos, we offer:
  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
  • Unlimited PTO. No rigid vacation banks, just a focus on delivery.
  • 401(k) matching and stock option opportunities to ensure our success is your success.
  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
  • Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don't.

Apply