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Full Time Pdk Engineer Jobs in Texas (NOW HIRING)

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Full Time Pdk Engineer information

What is the difference between Full Time Pdk Engineer vs Full Time ASIC Design Engineer?

AspectFull Time Pdk EngineerFull Time ASIC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; familiarity with PDKsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; strong digital design background
Work EnvironmentDesign houses, foundries, semiconductor companiesSemiconductor companies, design firms, integrated device manufacturers
Industry UsageUsed primarily in process design kit development and customizationUsed in designing and verifying integrated circuits and chips

While both roles require a background in VLSI and semiconductor processes, a Full Time Pdk Engineer focuses on developing and maintaining process design kits, whereas a Full Time ASIC Design Engineer concentrates on designing and verifying application-specific integrated circuits. The roles often overlap in industry but serve different stages of chip development.

Full Time Pdk Engineer jobs near you
Infographic showing various Full Time Pdk Engineer job openings in Texas as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

Senior/Principal Engineer with Signal/Power Integrity, Multiphysics, PDK/ADK Experience

Nityo Infotech

Austin, TX • On-site

$165K/yr

Full-time

Re-posted 26 days ago

Job description

Role: Senior/Principal Engineer with Signal/Power Integrity, Multiphysics, PDK/ADK Experience

Location: Austin, TX (HYBRID)

Job Type: FULL TIME

MUST HAVE: SI/PI - Signal Integrity /Power Integrity, Multiphysics simulations, Advanced packaging, Heterogeneous integration platforms, multi-material packages, PDK/ADK simulation collateral Experience

Job Description:

What You’ll Do

  • Own and execute hands-on SI/PI and multiphysics simulations for advanced 2.5D/3.0D heterogeneous integration and multi-material packages.
  • Perform modeling, extraction, and verification of high-speed interconnects, power delivery networks, thermal management, and mechanical stress across chiplets and advanced substrates.
  • Build and validate comprehensive ADK/PDK models (electrical, EM, thermal, mechanical) that accurately represent package-level behavior and enable system-level co-design.
  • Run end-to-end simulation workflows including EM extraction, S-parameter generation, PDN impedance analysis, crosstalk/eye diagram simulations, thermal/structural reliability checks, and co-simulation across domains.
  • Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight, etc.), OSATs, and foundries to develop, test, and refine package simulation flows.
  • Generate user guides, reference flows, scripts, and automation that make SI/PI/multiphysics enablement repeatable and accessible to design teams.
  • Stay current with next-gen interface standards (PCIe Gen6/7, CXL, UCIe, UALink, SerDes, HBM) and incorporate their requirements into package design methodologies.
  • Guide technical strategy for SI/PI flows, mentor junior engineers, and represent TIE in working groups, customer design reviews, and industry forums.

Required Qualifications:

  • BS in Electrical Engineering, Computer Engineering, Applied Physics, or related discipline.
  • 8+ years (Senior) / 12+ years (Principal) of direct, hands-on experience in signal integrity, power integrity, and multiphysics simulations for advanced packaging, 2.5D/3DIC, or heterogeneous integration platforms.
  • Strong expertise with EDA/EM/multiphysics tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Synopsys RaptorX, Siemens HyperLynx, Keysight ADS, COMSOL, CST Studio.
  • Proven ability to extract/package-level models (RLC, S-parameters, dielectric/thermal constants, warpage/stress data) and integrate them into design enablement flows.
  • Demonstrated experience creating and validating PDK/ADK simulation collateral spanning SI/PI, RF, thermal, and mechanical domains.
  • Hands-on scripting/automation skills (Python, Tcl, SKILL, etc.) to streamline simulation flows.
  • Startup DNA. You’re energized by ambiguity, act with urgency, and take personal ownership for outcomes. You make things happen.
  • Execution mindset. You have demonstrated experience working in a hands-on role driving progress across multiple initiatives without layers of management.
  • Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible with travel up to 30–50%.  Such arrangements are subject to University review and approval in relation to jurisdictional employment-related laws, rules, and regulations.

Preferred Qualifications:

  • MS or PhD in Electrical Engineering, Applied Physics, or related discipline.
  • Deep experience with multi-material packages (Si, glass, organics, Cu, RDL, TSV, hybrid bonding, etc.).
  • Expertise in system-level co-simulation spanning electrical, thermal, and mechanical domains for high-power/high-bandwidth-density packages.
  • Familiarity with industry standards (IEEE, JEDEC, OIF, UCIe, 3Dblox, JEP30) and experience contributing to working groups.
  • Background in high-speed interconnect modeling and compliance testing for PCIe, CXL, UCIe, SerDes, HBM, or similar standards.
  • Track record of technical publications, patents, or open-source contributions in SI/PI/multiphysics simulation and design enablement.