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Full Time Asic Rtl Design Engineer Jobs in Phoenix, AZ

RTL Design Engineer

Chandler, AZ · On-site

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

RTL Design Engineer

Phoenix, AZ

$105.65K - $200.34K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...

RTL Design Engineer

Chandler, AZ

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

The Role and Impact As a Senior RTL Design Engineer, you will play a pivotal role in developing Intel's next-generation microprocessors, contributing to groundbreaking technologies that drive ...

Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Senior Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Staff Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

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Requirements of an ASIC Design for Test Engineer include 5+ years of experience as an ASIC engineer and a BS or MS in Electrical or Computer Engineering (with relevant coursework on digital ...

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Full Time Asic Rtl Design Engineer information

See Phoenix, AZ salary details

$93.3K

$149.1K

$200.6K

How much do full time asic rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for full time asic rtl design engineer in Phoenix, AZ is $149,131.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,600.00 and $178,700.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Full Time ASIC RTL Design Engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.

What are some common challenges Full Time ASIC RTL Design Engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What are Full Time ASIC RTL Design Engineers?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Phoenix, AZ? The most popular types of Asic Rtl Design Engineer jobs in Phoenix, AZ are:
What job categories do people searching Full Time Asic Rtl Design Engineer jobs in Phoenix, AZ look for? The top searched job categories for Full Time Asic Rtl Design Engineer jobs in Phoenix, AZ are:
RTL Design Engineer

RTL Design Engineer

Broadcom, Inc.

Chandler, AZ • On-site

$127.10K - $203.40K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 8 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers


Job description

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Job Description:
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.
  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/SystemVerilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Job Requirements
  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications
  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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