STA Engineer
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
STA Engineer
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
Senior/Lead STA Engineer
Austin, TX · On-site
Own and drive full-chip and block-level STA from early implementation through final timing signoff ... Mentor junior and senior engineers and provide technical leadership on complex timing problems.
Senior/Lead STA Engineer
Austin, TX · On-site
Own and drive full-chip and block-level STA from early implementation through final timing signoff ... Mentor junior and senior engineers and provide technical leadership on complex timing problems.
STA Engineer
$184K - $324K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure ownership throughout the entire project. Develop and ...
STA Engineer
$184K - $324K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure ownership throughout the entire project. Develop and ...
GPU Design Implementation, Static Timing Analysis Engineer
Austin, TX · On-site
$120 - $145/hr
Austin, TX or San Jose, CA. onsite strongly preferred Need: "STA engineer with strong PrimeTime ... and/or full chip implementation with the latest industry P&R/STA flows and tools. Sign-off ...
GPU Design Implementation, Static Timing Analysis Engineer
Austin, TX · On-site
$120 - $145/hr
Austin, TX or San Jose, CA. onsite strongly preferred Need: "STA engineer with strong PrimeTime ... and/or full chip implementation with the latest industry P&R/STA flows and tools. Sign-off ...
Senior SoC STA Engineer
San Diego, CA · On-site
$144K - $148K/yr
Job Summary We are seeking a highly experienced Senior SoC STA Engineer to own chip-level timing ... Drive timing closure at both block and full-chip levels through critical path analysis, ECO ...
Senior SoC STA Engineer
San Diego, CA · On-site
$144K - $148K/yr
Job Summary We are seeking a highly experienced Senior SoC STA Engineer to own chip-level timing ... Drive timing closure at both block and full-chip levels through critical path analysis, ECO ...
Austin, TX or San Jose, CA. onsite strongly preferred Need: "STA engineer with strong PrimeTime ... and/or full chip implementation with the latest industry P&R/STA flows and tools. * Sign-off ...
Austin, TX or San Jose, CA. onsite strongly preferred Need: "STA engineer with strong PrimeTime ... and/or full chip implementation with the latest industry P&R/STA flows and tools. * Sign-off ...
STA Engineer
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
STA Engineer
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
Sr. Staff Physical Design Timing Engineer (STA)
Mountain View, CA · On-site
$220K - $270K/yr
Run full-chip STA and accurately project the timing summary across scenarios. * Leverage Tempus ... Bachelor's degree in Electrical Engineering or Computer engineering * 12 years of Physical Design ...
Sr. Staff Physical Design Timing Engineer (STA)
Mountain View, CA · On-site
$220K - $270K/yr
Run full-chip STA and accurately project the timing summary across scenarios. * Leverage Tempus ... Bachelor's degree in Electrical Engineering or Computer engineering * 12 years of Physical Design ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$217K - $267K/yr
Run full-chip STA and accurately project the timing summary across scenarios. * Leverage Tempus ... Bachelor's degree in Electrical Engineering or Computer engineering * 12 years of Physical Design ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$217K - $267K/yr
Run full-chip STA and accurately project the timing summary across scenarios. * Leverage Tempus ... Bachelor's degree in Electrical Engineering or Computer engineering * 12 years of Physical Design ...
STA Engineer
$129K - $194K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
STA Engineer
$129K - $194K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring ... Working knowledge of Extraction and STA methodology and tools * Working knowledge of Computer ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring ... Working knowledge of Extraction and STA methodology and tools * Working knowledge of Computer ...
Senior Static Timing Analysis (STA) Engineer Important: if an employer asks you to log into their ... Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery ...
Senior Static Timing Analysis (STA) Engineer Important: if an employer asks you to log into their ... Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery ...
SoC Timing (Static Timing Analysis/STA) Engineer, HBM Richardson, Texas, United States of America
Richardson, TX · On-site
JR101355 SoC Timing (Static Timing Analysis/STA) Engineer, HBM Our vision is to transform how the ... Drive timing closure at block, subsystem, and full-chip levels through critical path analysis ...
SoC Timing (Static Timing Analysis/STA) Engineer, HBM Richardson, Texas, United States of America
Richardson, TX · On-site
JR101355 SoC Timing (Static Timing Analysis/STA) Engineer, HBM Our vision is to transform how the ... Drive timing closure at block, subsystem, and full-chip levels through critical path analysis ...
Senior Static Timing Analysis (STA) Engineer Important: if an employer asks you to log into their ... Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery ...
Senior Static Timing Analysis (STA) Engineer Important: if an employer asks you to log into their ... Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery ...
STA Engineer
$129K - $194K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
STA Engineer
$129K - $194K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC ... Full chip and block level timing closure/constraints ownership throughout the entire project. You ...
Principal Physical Design Engineer, STA
San Jose, CA · On-site
$159K - $164K/yr
Overview As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in ... Provide actionable timing feedback at both block and full-chip levels, including root cause ...
Principal Physical Design Engineer, STA
San Jose, CA · On-site
$159K - $164K/yr
Overview As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in ... Provide actionable timing feedback at both block and full-chip levels, including root cause ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... Layout design background is a plus Working knowledge of Extraction and STA methodology and tools ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... Layout design background is a plus Working knowledge of Extraction and STA methodology and tools ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... Layout design background is a plus Working knowledge of Extraction and STA methodology and tools ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... Layout design background is a plus Working knowledge of Extraction and STA methodology and tools ...
Lead STA Engineer
San Jose, CA · On-site
$200K - $250K/yr
... STA Engineer to join our growing team. The Timing Lead will work on timing convergence and ... Experience in full chip sign-off budgeting * Knowledge of circuit design, device physics, deep sub ...
Lead STA Engineer
San Jose, CA · On-site
$200K - $250K/yr
... STA Engineer to join our growing team. The Timing Lead will work on timing convergence and ... Experience in full chip sign-off budgeting * Knowledge of circuit design, device physics, deep sub ...
Physical Design Engineer (Top-Level / Full-Chip) - AS
San Jose, CA · On-site
$159K - $164K/yr
STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only ... RTL Engineers Required attributes: TCL/PERL Scripting Proficiency in related EDA Tools Full ...
New
Physical Design Engineer (Top-Level / Full-Chip) - AS
San Jose, CA · On-site
$159K - $164K/yr
STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only ... RTL Engineers Required attributes: TCL/PERL Scripting Proficiency in related EDA Tools Full ...
New
Full Chip Sta Engineer information
What are popular job titles related to Full Chip Sta Engineer jobs?
For Full Chip Sta Engineer jobs, the most frequently searched job titles are:
STA Engineer
Austin, TX • On-site
Apple
• Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 9 days ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
Job description
Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers.
Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.
Description
As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis.
Minimum Qualifications
Bachelors Degree + 0 Years of Experience.
Preferred Qualifications
Strong fundamentals in the area of Digital design
Familiarity with ASIC design timing concepts
Proficient in scripting languages (TCL, Python and Perl)
Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus
Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
Self-starter and highly motivated
Ability to communicate optimally across all internal groups
Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.
Description
As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis.
Minimum Qualifications
Bachelors Degree + 0 Years of Experience.
Preferred Qualifications
Strong fundamentals in the area of Digital design
Familiarity with ASIC design timing concepts
Proficient in scripting languages (TCL, Python and Perl)
Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus
Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
Self-starter and highly motivated
Ability to communicate optimally across all internal groups
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976