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Amd Chip Design Engineer Jobs (NOW HIRING)

TenX Semi

Chip Design Engineer

San Francisco, CA · On-site

$150 - $200/hr

San Francisco Bay Area, CA · Hybrid · Full-time We are looking for a Chip Design Engineer who ... Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell ...

Ricursive

Chip Design Engineer

Palo Alto, CA · On-site

$250/hr

ABOUT THE ROLE Physical design is where AI-driven chip design gets graded: every placement, clock ... To close the loop between our AI and real silicon, we need an engineer who knows every step of the ...

New

Agentrys

$125 - $150/hr

Role Description This is a full-time, on-site position for a Solutions Engineer, AI for Chip Design based in San Jose, CA or Hsinchu, Taiwan. In this role, you will: * Deploy agentic AI systems into ...

Ricursive

Software Engineer, Chip Design

Palo Alto, CA · On-site

$200 - $250/hr

Comfortable using modern AI-assisted development tools to navigate complex codebases, debug problems, and accelerate engineering workflows. * Working understanding of the digital chip design flow ...

New

Advanced Micro Devices

$200 - $250/hr

At AMD, we believetechnology has the power to solve the world's most important challenges. From ... You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ...

Socket.dev

Packaging Design Engineer

San Jose, CA · On-site

$150 - $200/hr

The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and ...

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Amd Chip Design Engineer information

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How much do amd chip design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for amd chip design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Amd Chip Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Chip Design Engineer

San Francisco, CA • On-site

TenX Semi
See more jobs at TenX Semiexternal

$150 - $200/hr

Other

Posted 8 days ago

Job description

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design Engineer who works on strategic customer engagements, developing custom IP and optimizing designs for power, performance, and area. You will collaborate closely with our AI systems, providing the domain expertise that ensures AI-generated designs meet real-world requirements.

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into production at the world's leading technology companies.

What You Will Do
  • Design RTL for Customer Projects: Implement RTL for strategic customer engagements. You will write clean, synthesizable, timing-aware Verilog/SystemVerilog.
  • Optimize for PPA: Analyze and optimize designs for power, performance, and area. Your optimizations will contribute to royalty-generating designs.
  • Support Synthesis and Timing: Work through synthesis and timing closure. You understand what makes RTL synthesizable and how to fix timing violations.
  • Improve AI-Generated Designs: Review and enhance AI-generated RTL for production quality. Your feedback will improve model accuracy.
  • Develop Reference Implementations: Create high-quality reference designs that become training data for our AI models.
  • Implement Protocol Blocks: Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements.
What You Bring (Required)
  • RTL Design Experience: You have 5+ years of experience designing production RTL. You write clean, readable, synthesizable Verilog/SystemVerilog.
  • Micro-Architecture Understanding: You have solid understanding of pipeline design, FSMs, arbitration, and data flow. You can translate architecture specs into RTL.
  • Synthesis Awareness: You have experience with synthesis tools (Design Compiler, Genus). You understand what makes RTL timing-friendly.
  • Debug Skills: You can read waveforms, trace signal paths, and debug complex logic issues. You have experience with Verdi, SimVision, or similar tools.
  • PPA Intuition: You understand power-performance-area tradeoffs. You can make informed design decisions based on PPA goals.
  • Collaborative Mindset: You work well with verification engineers, architects, and AI engineers. You communicate clearly and give/receive feedback well.
Bonus Points (Preferred)
  • Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, MediaTek).
  • Protocol implementation experience (PCIe, DDR, AXI, AHB, APB, CHI).
  • Physical design awareness (floor planning, clock tree, routing congestion).
  • Background in accelerator, SoC, or high-performance computing design.
  • Familiarity with AI/ML concepts and interest in AI-assisted design.
  • MS in Electrical Engineering or Computer Science.
Why Join Us

You will be at the forefront of AI-assisted chip design—a fundamental transformation in how chips are built. Your designs will go into production at top tech companies. You'll learn cutting-edge AI while applying your chip design expertise, building skills that will define the future of the industry.

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