System Chip Design Engineer Jobs (NOW HIRING)

Ricursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence.

Physical design is where AI-driven chip design gets graded: every placement, clock tree, routing, and optimization our systems produce must ultimately converge to signoff-clean GDSII in an advanced node. To close the loop between our AI and real silicon, we need an engineer who knows every step of the flow cold, from synthesis through tapeout, and who has personally fought complex blocks to closure at an advanced node. Your expertise becomes the ground truth our self-improving systems learn from and are measured against.

You will participate in developing the architecture of Ricursive's physical design flow end to end, both top-down (chip-level planning, partitioning, budgeting, hierarchical signoff) and bottom-up (block construction and closure feeding full-chip assembly), and you will pair that flow with AI tooling, ours and the industry's, to make each iteration faster than the last. This is a small and early team, so the methodology and infrastructure are still being defined; you will define them.

• Architect Ricursive's RTL-to-GDSII flow across block, subsystem, and full-chip levels, covering synthesis, DFT insertion, floorplanning, PDN design, placement, CTS, routing, and all electrical and physical signoff. Build both the top-down hierarchical plan (partitioning, pin and bump planning, timing and power budgets, ILM/ETM abstraction) and the bottom-up block closure path that assembles cleanly at the top.
• Own timing, power, and physical closure of the most complex, PPA-critical blocks in advanced nodes, driving multi-mode multi-corner convergence in PrimeTime/Tempus, EM/IR signoff in RedHawk/Voltus, and DRC/LVS closure in Calibre/Pegasus through final ECOs and tapeout.
• Deploy and extend AI tooling across the flow, including AI-driven design-space optimization in DTCO, ML-based PPA improvement, and LLM agents for run orchestration, log triage, constraint validation, and ECO generation, with measurable reductions in iteration count and time-to-closure.
• Work closely with our research team to train and test self-improving design models and agents, defining what "good" looks like at every flow stage and encoding signoff-quality judgment into automated reward and checking infrastructure.
• Build the automation backbone in Python and Tcl: reproducible flow orchestration, regression and QoR-tracking dashboards, and correct-by-construction checks that make convergence visible and repeatable across the team.
• Partner with Architect, RTL, DFT, and foundry/design-service teams to structure designs for implementability and feed early physical feedback into microarchitecture and floorplan decisions.

• BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.
• 10+ years of hands-on physical design experience spanning every step of the flow (synthesis, floorplanning, PDN, placement, CTS, routing, STA, extraction, power/EM/IR analysis, physical verification, LEC, and ECO), including experience architecting hierarchical flows both top-down and bottom-up.
• Day-one fluency in at least one production implementation and signoff stack with commercial EDA tools and strong Tcl and Python scripting.
• Track record of successful chip design and tapeout: owned closure of complex blocks, subsystems, or full chips through complete signoff in advanced technology nodes, on silicon that taped out and shipped to production.
• Demonstrated and quantified the PPA benefit of using AI/ML tooling to accelerate physical design, such as AI-driven optimization, ML QoR prediction, or LLM-based flow automation.

• Master's or PhD in EE, CE, CS, or a related field, with a focus on VLSI, physical design, or EDA/CAD algorithms.
• Deep expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including multi-voltage domain (UPF) design and 2.5D/3D integration with bump/RDL planning.
• Experience applying ML to chip design, such as RL and learning-based placement and optimization, building AI copilots or agents with frontier models, or contributing physical design expertise to AI-for-EDA initiatives.
• Publications at major conferences (e.g., DAC, ICCAD, ISPD, DATE) demonstrating research strength in physical design or ML-for-EDA.