Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation. Description * Participating in the physical ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation. Description * Participating in the physical ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
ASIC Chip Design Lead
Saratoga, CA · On-site
The company is in execution mode and has a world-class engineering team with decades of experience ... Full-Chip Integration & Signoff * Own full-chip RTL integration and block roll-up * Run chip-level ...
ASIC Chip Design Lead
Saratoga, CA · On-site
The company is in execution mode and has a world-class engineering team with decades of experience ... Full-Chip Integration & Signoff * Own full-chip RTL integration and block roll-up * Run chip-level ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Own full-chip RTL integration and block roll-up * Run chip-level synthesis, define constraints, and ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Own full-chip RTL integration and block roll-up * Run chip-level synthesis, define constraints, and ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Perform full-chip integration, verification, and system-level validation following standard ASIC ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Perform full-chip integration, verification, and system-level validation following standard ASIC ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Perform full-chip integration, verification, and system-level validation following standard ASIC ...
Quick apply
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Perform full-chip integration, verification, and system-level validation following standard ASIC ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Full Chip Integration Engineer information
See salary details
$44.5K - $56.2K
0% of jobs
$56.2K - $68K
2% of jobs
$68K - $79.7K
3% of jobs
$79.7K - $91.4K
7% of jobs
$91.4K - $103.1K
10% of jobs
$104.7K is the 25th percentile. Wages below this are outliers.
$103.1K - $114.9K
16% of jobs
The median wage is $121.3K / yr.
$114.9K - $126.6K
21% of jobs
$136.9K is the 75th percentile. Wages above this are outliers.
$126.6K - $138.3K
18% of jobs
$138.3K - $150K
10% of jobs
$150K - $161.8K
7% of jobs
$161.8K - $173.5K
5% of jobs
$44.5K
$124.3K
$173.5K
How much do full chip integration engineer jobs pay per year?
As of Sep 10, 2026, the average yearly pay for full chip integration engineer in the United States is $124,275.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,000.00 and $140,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Full Chip Integration Engineer jobs?
Cities with the most Full Chip Integration Engineer job openings:
What states have the most Full Chip Integration Engineer jobs?
States with the most job openings for Full Chip Integration Engineer jobs include:
What are popular job titles related to Full Chip Integration Engineer jobs?
For Full Chip Integration Engineer jobs, the most frequently searched job titles are:
CPU Full-chip Physical Integration Engineer
Beaverton, OR • On-site
Apple •
Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 15 hours ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.
• Full chip floorplan, area optimizations, block partitioning and pin placements
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
• Develop and validate Power Grid, including routability analysis
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
• Work with the SOC team to meet IP technical and delivery requirements
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
• Scripting to automate tasks and improve debug efficiency
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with scripting in Perl or TCL
Preferred Qualifications
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
Experience in developing and implementing Power Grid and Clock specifications
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
Solid understanding of CMOS circuit design. Layout design background is a plus
Working knowledge of Extraction and STA methodology and tools
Working knowledge of Computer Architecture
Ability to work well in a team, being an excellent problem solver, and self motivated
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.
• Full chip floorplan, area optimizations, block partitioning and pin placements
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
• Develop and validate Power Grid, including routability analysis
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
• Work with the SOC team to meet IP technical and delivery requirements
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
• Scripting to automate tasks and improve debug efficiency
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with scripting in Perl or TCL
Preferred Qualifications
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
Experience in developing and implementing Power Grid and Clock specifications
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
Solid understanding of CMOS circuit design. Layout design background is a plus
Working knowledge of Extraction and STA methodology and tools
Working knowledge of Computer Architecture
Ability to work well in a team, being an excellent problem solver, and self motivated
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976