As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Own full-chip RTL integration and block roll-up * Run chip-level synthesis, define constraints, and ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Own full-chip RTL integration and block roll-up * Run chip-level synthesis, define constraints, and ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Principal Layout Design Engineer
Durham, NC · On-site
$182K - $273K/yr
Collaborate with the Place & Route (P&R) team to resolve full-chip integration issues. * Develop ... Coordinate with circuit engineers located in different regions and time zones. * Support and assist ...
Principal Layout Design Engineer
Durham, NC · On-site
$182K - $273K/yr
Collaborate with the Place & Route (P&R) team to resolve full-chip integration issues. * Develop ... Coordinate with circuit engineers located in different regions and time zones. * Support and assist ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Full Chip Integration Engineer information
See salary details
$44.5K - $56.2K
0% of jobs
$56.2K - $68K
2% of jobs
$68K - $79.7K
3% of jobs
$79.7K - $91.4K
7% of jobs
$91.4K - $103.1K
10% of jobs
$104.7K is the 25th percentile. Wages below this are outliers.
$103.1K - $114.9K
16% of jobs
The median wage is $121.3K / yr.
$114.9K - $126.6K
21% of jobs
$136.9K is the 75th percentile. Wages above this are outliers.
$126.6K - $138.3K
18% of jobs
$138.3K - $150K
10% of jobs
$150K - $161.8K
7% of jobs
$161.8K - $173.5K
5% of jobs
$44.5K
$124.3K
$173.5K
How much do full chip integration engineer jobs pay per year?

Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan, area optimizations, block partitioning and pin placements• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)• Develop and validate Power Grid, including routability analysis• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout• Work with the SOC team to meet IP technical and delivery requirements• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis• Scripting to automate tasks and improve debug efficiency
Minimum BS and 10+ years of relevant industry experienceExperience with scripting in Perl or TCL
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical VerificationExperience in developing and implementing Power Grid and Clock specificationsSolid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFMSolid understanding of verification tools such as Conformal LP, LEC, RedHawk, CalibreSolid understanding of CMOS circuit design. Layout design background is a plusWorking knowledge of Extraction and STA methodology and toolsWorking knowledge of Computer ArchitectureAbility to work well in a team, being an excellent problem solver, and self motivated
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976