San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
Santa Clara, CA · On-site
$159K - $195K/yr
... full chip integration - ensuring robust and high-performance connectivity across complex SoC ... S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or ...
Santa Clara, CA · On-site
$159K - $195K/yr
... full chip integration - ensuring robust and high-performance connectivity across complex SoC ... S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or ...
San Jose, CA · On-site
$200K - $250K/yr
Full-chip integration : floorplanning, power planning, macro/hard-IP placement, and block ... Technical leadership : mentor block-level PD engineers on convergence best practices; set ...
San Jose, CA · On-site
$200K - $250K/yr
Full-chip integration : floorplanning, power planning, macro/hard-IP placement, and block ... Technical leadership : mentor block-level PD engineers on convergence best practices; set ...
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Quick apply
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Sunnyvale, CA · On-site
$170K - $230K/yr
Sr. Full Chip Physical Verification Engineer (Silicon Engineering) Sunnyvale, CA SpaceX is actively ... Experience in IP integration (memories, I/O, analog IPs, SerDes, DDR, etc.). * Expertise in DRC ...
Sunnyvale, CA · On-site
$170K - $230K/yr
Sr. Full Chip Physical Verification Engineer (Silicon Engineering) Sunnyvale, CA SpaceX is actively ... Experience in IP integration (memories, I/O, analog IPs, SerDes, DDR, etc.). * Expertise in DRC ...
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Irvine, CA · On-site
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Quick apply
Irvine, CA · On-site
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Perform full-chip SoC integration, including IP integration, clock/reset domain management, power ...
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
San Jose, CA · On-site
$185K - $230K/yr
As a Principal Engineer on the Physical Design team, you will own the backend implementation of ... Hands-on experience with hierarchical implementation and full-chip integration of large designs ...
San Jose, CA · On-site
$185K - $230K/yr
As a Principal Engineer on the Physical Design team, you will own the backend implementation of ... Hands-on experience with hierarchical implementation and full-chip integration of large designs ...
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Quick apply
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
Quick apply
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R ... integration. * Debug complex PV violations across layout, routing, macros, IP, power grid, rule ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$110K - $140K/yr
Perform full-chip integration and verification * Support chip bring-up, validation, and silicon debugging * Collaborate with algorithm and application engineers on image tuning, optimization, and ...
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
$44.5K - $56.2K
0% of jobs
$56.2K - $68K
2% of jobs
$68K - $79.7K
3% of jobs
$79.7K - $91.4K
7% of jobs
$91.4K - $103.1K
10% of jobs
$104.7K is the 25th percentile. Wages below this are outliers.
$103.1K - $114.9K
16% of jobs
The median wage is $121.3K / yr.
$114.9K - $126.6K
21% of jobs
$136.9K is the 75th percentile. Wages above this are outliers.
$126.6K - $138.3K
18% of jobs
$138.3K - $150K
10% of jobs
$150K - $161.8K
7% of jobs
$161.8K - $173.5K
5% of jobs
$44.5K
$124.3K
$173.5K
Cities with the most Full Chip Integration Engineer job openings:
States with the most job openings for Full Chip Integration Engineer jobs include:
For Full Chip Integration Engineer jobs, the most frequently searched job titles are:
San Jose, CA • On-site
$2.0K/mo
Other
Medical, Dental, Vision
Re-posted 19 days ago
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job SummaryEtched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Key ResponsibilitiesOwn full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between top level and blocks.
Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.
10+ years of previous experience with chip planning, top level PD, floorplanning
Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
Experience with Pegasus or Calibre for physical verification signoff
Experience with hierarchical timing budgeting, constraint management, and ECO closure
Experience with Cadence Innovus for top-level assembly, routing, and layout fixes
Deeply creative and able to think from first principles
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
