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Full Chip Integration Engineer Jobs in New York (NOW HIRING)

Capital One

Senior Integration Engineer

New York, NY · On-site

$113K - $153K/yr

Senior Integration Engineer Do you love building and pioneering in the technology space? Do you ... Eligibility varies based on full or part-time status, exempt or non-exempt status, and management ...

GlobalFoundries

Quantum TSV Integration Engineer

New York, NY · On-site

$113K - $153K/yr

About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a ... Assembly and integration engineers * Device / qubit / system engineers * Ensure co-optimization of ...

Capital One

Lead Integration Engineer

New York, NY · On-site

$112K - $147K/yr

Lead Integration Engineer Do you love building and pioneering in the technology space? Do you enjoy ... Eligibility varies based on full or part-time status, exempt or non-exempt status, and management ...

Capital One

Lead Integration Engineer

New York, NY · On-site

$112K - $147K/yr

Lead Integration Engineer Do you love building and pioneering in the technology space? Do you enjoy ... Eligibility varies based on full or part-time status, exempt or non-exempt status, and management ...

Capital One

Senior Integration Engineer

New York, NY · On-site

$114K - $157K/yr

Senior Integration Engineer Do you love building and pioneering in the technology space? Do you ... Eligibility varies based on full or part-time status, exempt or non-exempt status, and management ...

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Full Chip Integration Engineer information

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Infographic showing various Full Chip Integration Engineer job openings in New York as of August 2026, with employment types broken down into 89% Full Time, and 11% Contract. Highlights an 100% In-person job distribution.

US_East | Electrical / Electronics & Semiconductors Engineer_L3

NJ • On-site

Redolent, Inc.
IT Services • 51 - 200 employees
Learn more about Redolent, Inc.external

Contractor

Posted 9 days ago

Job description

Description:
"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential
TMR ID: AUTUM3
Role: ASIC CAD/EDA Flow/Methodology Developer
Work location: Irvine/San Jose (CA)
Background and Meet and Greet: MANDATORY
Job Description:
"• 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
• Great understanding of CAD flows and tools related to ASIC/SOC methodologies
• Excellent programming skills in languages: SKILL, Perl; Python is a plus
• Strong fundamentals in software development
• Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
• Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
• Excellent communication and interpersonal skills
"
Key Responsibilities:
"• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
• Experience in Block-level and Full-chip integration.
• Understanding constraints and fixing design/timing techniques
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
• Understanding constraints and fixing design/timing techniques
• Understanding SI prevention, fixing methodology and implementation
• Proficient in Synopsys tools such ICC/ICC2, Cadence Innovus/Virtuoso
• Experience in Design Automation and UNIX system.
"
What are the Mandatory skills and skill proficiencies required for this position?
"Python (Preference: 5)
Synopsys/Cadence EDA tools/flows (Preference: 5)
TCL/Perl (Preference: 5)"
What are the Optional skills and skill proficiencies for this position?
The following details must accompany your submission:
First Name, Middle name, and Last Name:
City and State:
Open to Relocate?
Rate:
Availability:
Phone #:
Mobile #:
Email address:
Visa type:
Visa Expiration Date:
Hiring Status:
Mariana Zarate - ERM
Capgemini North America
Tel.: +1 888-229-2961"
Additional Details
  • Global Grade : C
  • Named Job Posting? (if Yes - needs to be approved by SCSC) : No
  • Remote work possibility : No
  • Global Role Family : 61405 (P) Products & Systems Engineering
  • Global Technical Skills Family : 60614 (T) Electrical, Electronics & Semiconductors
  • Local Role Name : Role: ASIC CAD/EDA Flow/Methodology Developer
  • Local Skills : Julie Skidmore
  • Languages Required: : English
Redolent logo

About Redolent

Sourced by ZipRecruiter

Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

San Jose, CA, US

Year founded

2008

Social media

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