We are hiring a Photonics Hardware Validation Engineer to join our Validation team to drive ... You will need to understand our chip specifications well so that you can take responsibility for ...
We are hiring a Photonics Hardware Validation Engineer to join our Validation team to drive ... You will need to understand our chip specifications well so that you can take responsibility for ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Senior Memory Validation Engineer - DDR/HBM, Silicon Bring-up | Mountain View, CA (On-site)
Mountain View, CA · On-site
Senior Memory Validation Engineer DDR/HBM, Silicon Bring-up BrickRed Systems Mountain View ... This role places you at the center of hands-on silicon chip validation for one of the industry ...
Quick apply
Senior Memory Validation Engineer - DDR/HBM, Silicon Bring-up | Mountain View, CA (On-site)
Mountain View, CA · On-site
Senior Memory Validation Engineer DDR/HBM, Silicon Bring-up BrickRed Systems Mountain View ... This role places you at the center of hands-on silicon chip validation for one of the industry ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring ... Develop and validate Power Grid, including routability analysis. * Drive custom layout integration ...
CPU Full-chip Physical Integration Engineer
Beaverton, OR · On-site
$143K - $147K/yr
CPU Full-chip Physical Integration Engineer Apple's Silicon Engineering Group (SEG) is hiring ... Develop and validate Power Grid, including routability analysis. * Drive custom layout integration ...
WI · On-site
Full-chip integration and verification * Silicon bring-up, validation and debug Qualifications * Minimum MSEE + at least 7 yrs. of digital design experience * Expertise in RTL design and verification ...
WI · On-site
Full-chip integration and verification * Silicon bring-up, validation and debug Qualifications * Minimum MSEE + at least 7 yrs. of digital design experience * Expertise in RTL design and verification ...
Sr. Digital Design Engineer
Irvine, CA · On-site
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Quick apply
Sr. Digital Design Engineer
Irvine, CA · On-site
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Sr. Digital Design Engineer
Irvine, CA · On-site
$120K - $150K/yr
Full-chip integration and verification. * Chip bring-up, validation, and debugging * Work with algorithm and application engineers for image tuning and qualification * Silicon validation, debugging ...
Photonics Hardware Validation Engineer
Mountain View, CA · On-site
$177K - $240K/yr
We are hiring a Photonics Hardware Validation Engineer to join our Validation team to drive ... You will need to understand our chip specifications well so that you can take responsibility for ...
Photonics Hardware Validation Engineer
Mountain View, CA · On-site
$177K - $240K/yr
We are hiring a Photonics Hardware Validation Engineer to join our Validation team to drive ... You will need to understand our chip specifications well so that you can take responsibility for ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Embedded Engineer (Multiple Openings) Location: Chandler, AZ (Day 1 Onsite) Duration: Fulltime with ... Develop/Enhance test content for PM and Full chip validation. * Do triage and debug of failures We ...
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Embedded Engineer (Multiple Openings) Location: Chandler, AZ (Day 1 Onsite) Duration: Fulltime with ... Develop/Enhance test content for PM and Full chip validation. * Do triage and debug of failures We ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee ...
Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$2.0K/mo
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip ...
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... • Develop and validate Power Grid, including routability analysis • Drive custom layout ...
Full Chip Validation Engineer information
See salary details
$22.60 - $27.64
2% of jobs
$27.64 - $32.69
6% of jobs
$32.69 - $37.74
13% of jobs
$39.32 is the 25th percentile. Wages below this are outliers.
$37.74 - $42.79
13% of jobs
$42.79 - $47.84
11% of jobs
The median wage is $50.36 / hr.
$47.84 - $52.88
12% of jobs
$52.88 - $57.93
9% of jobs
$61.82 is the 75th percentile. Wages above this are outliers.
$57.93 - $62.98
13% of jobs
$62.98 - $68.03
13% of jobs
$68.03 - $73.08
6% of jobs
$73.08 - $78.13
3% of jobs
$22
$51
$78
How much do full chip validation engineer jobs pay per hour?
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Photonics Hardware Validation Engineer
Mountain View, CA • On-site
Full-time
Re-posted 24 days ago
Job description
In this role, you will design, develop, and build photonic test systems that are critical to the characterization and validation of our products. You will collaborate closely with device, hardware, software, and digital and analog design teams to support the end-to-end development, validation, and qualification of photonic systems and their key components.
Join a tight-knit team where each individual's contributions directly impact the success of the company and our innovative products. At Lightmatter, you'll have the opportunity to work with people who love to build and thrive in technically diverse environments where great ideas are valued and prioritized.
We are hiring a Photonics Hardware Validation Engineer to join our Validation team to drive photonics testing, characterization and validation of our silicon photonics-based optical Interconnect Products.
Responsibilities- You will need to understand our chip specifications well so that you can take responsibility for chip bring-up, testing, and validation of our next-generation Optical Interconnect products. This includes supporting the development of chip validation plans aligned to product specifications, xDVT, and interoperability testing.
- You will be required to contribute to test plan development, test bench configuration planning, setup of lab test equipment, and troubleshooting of validation setups to enable successful chip bring-up and testing.
- You will work within the product validation team on electro-optic, link-level testing in our lab using industry-standard practices and equipment.
- Bachelor's degree in Electrical Engineering, Physics, or a related field.
- Hands-on experience with standard bench test equipment for data communications, including electro-optic link testing and characterization.
- Experience in the data communications field, specifically in electro-optic link-level testing and characterization in a lab environment.
- Familiarity with PCB design, including hardware testing and debugging of electro-optic circuits.
- Ability to work closely with Design Engineers, Software Engineers, and broader cross-functional teams to quickly gain knowledge of Lightmatter products and drive execution of chip bring-up and validation in our lab.
- Basic scripting skills for automation of lab tests including analysis of results and report generation.
- Solid understanding of electrical and optical blocks in transmitters and receivers to enable efficient chip bring-up and link testing.
- Ability to troubleshoot and debug the electrical optical building blocks in a transceiver to triage bugs and root-cause performance gaps.
- PhD is a plus
- Experience with high-speed data communication systems, including NRZ and PAM4 signaling.
- Familiarity with industry standards such as IEEE, OIF-CEI, or similar for data communication systems.
- Proficiency in Python, MATLAB, or similar tools for scripting and automation.
- Strong documentation skills to develop clear test plans, reports, and technical presentations.
- Prior experience in leading or mentoring junior engineers in lab validation and testing workflows.