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Full Chip Asic Verification Engineer Jobs (NOW HIRING)

... engineers to stay abreast of the specification and implementation of ASIC blocks, developing ... Develop block-level, sub-system and full-chip verification environment and tests to implement test ...

... engineers to stay abreast of the specification and implementation of ASIC blocks, developing ... Develop block-level, sub-system and full-chip verification environment and tests to implement test ...

Verification Engineer

Santa Clara, CA ยท On-site

$160K/yr

ASIC Verification Description * Here, you will be working at the heart of our chip design efforts ... full chip. * We are working daily to ensure the quality of the SOC by working closely with the team ...

Verification Engineer

Santa Clara, CA ยท On-site

$160K/yr

ASIC Verification Description * Here, you will be working at the heart of our chip design efforts ... full chip. * We are working daily to ensure the quality of the SOC by working closely with the team ...

Custom SOC IP Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip ... S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent ...

Custom SOC IP Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip ... S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or ...

Custom SOC IP Verification Engineer

Santa Clara, CA ยท On-site

$159K - $195K/yr

Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip ... S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent ...

Custom SOC IP Verification Engineer

Santa Clara, CA ยท On-site

$159K - $195K/yr

Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip ... S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or ...

ASIC Verification Engineer

Irvine, CA ยท On-site

$125 - $150/hr

You will work closely with marketing, architecture, firmware, physical and layout teams on full ... Understand chip architecture, microarchitecture and design specification. * Develop advanced ...

You willworkclosely with marketing, architecture, firmware, physical and layout teams on full ... Understand chip architecture, microarchitecture and design specification. Develop advanced ...

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Full Chip Asic Verification Engineer information

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$88K

$156.1K

$207K

How much do full chip asic verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for full chip asic verification engineer in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

What are popular job titles related to Full Chip Asic Verification Engineer jobs?

For Full Chip Asic Verification Engineer jobs, the most frequently searched job titles are:

Sr. Asic Design Verification Engineer

Austin, TX โ€ข On-site

VentureSoft Global
501 - 1,000 employees

$134K - $164K/yr

Other

Re-posted 17 days ago


Job description

Job Title: Senior ASIC Design Verification Engineer
Location: Austin, TX (Onsite/Hybrid)
Experience: 15+ Years
Job Summary
We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.
Primary Skills (Must Have)
  • SystemVerilog & UVM
  • Constrained Random Verification (CRV)
  • Functional Coverage & Coverage Closure
  • RTL Debug & ASIC/SoC Verification
Key Responsibilities
  • Develop UVM/SystemVerilog verification environments.
  • Create test plans, testbenches, sequences, scoreboards, and checkers.
  • Perform block-level and full-chip ASIC/SoC verification.
  • Execute constrained-random and directed testing.
  • Debug RTL issues and drive functional coverage closure.
  • Collaborate with design, architecture, and validation teams.
  • Support regression, verification signoff, and tape-out activities.
Preferred Skills
  • CPU/Processor or Memory Subsystem Verification
  • SVA (SystemVerilog Assertions)
  • ARM, RISC, AI/ML Accelerator, or GPU verification
  • Experience with VCS, Questa, or Xcelium
  • Python or C/C++
Education
Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.