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Fpga Low Latency Trading Jobs (NOW HIRING)

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

... low-latency trading applications * Develop simulation testbenches and functional verification ... Work closely with senior FPGA engineers and the trading infrastructure team to understand latency ...

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Fpga Low Latency Trading information

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$70K

$147.1K

$210.5K

How much do fpga low latency trading jobs pay per year?

As of Sep 2, 2026, the average yearly pay for fpga low latency trading in the United States is $147,056.00, according to ZipRecruiter salary data. Most workers in this role earn between $123,000.00 and $169,500.00 per year, depending on experience, location, and employer.

What is an FPGA low latency trading engineer?

An FPGA Low Latency Trading engineer is a specialist who designs, develops, and optimizes hardware solutions using Field Programmable Gate Arrays (FPGAs) to achieve ultra-fast processing speeds in financial trading systems. Their primary goal is to minimize latency—the delay between receiving market data and executing trades—often working closely with software engineers and traders. They use hardware description languages like VHDL or Verilog to implement trading algorithms directly in hardware, enabling faster performance compared to traditional software-based systems. These engineers are crucial in high-frequency trading (HFT) environments, where microseconds can make a significant difference in profitability.

What are the key skills and qualifications needed to thrive as an FPGA low latency trading engineer?

To thrive as an FPGA Low Latency Trading Engineer, you need expertise in digital design (VHDL/Verilog), hardware debugging, and a solid understanding of high-frequency trading systems, often supported by a degree in electrical engineering or computer science. Familiarity with FPGA development tools (such as Xilinx Vivado or Intel Quartus), scripting languages, and experience with network protocols (e.g., Ethernet) are typically required. Strong analytical thinking, problem-solving abilities, and effective communication help you collaborate with traders and software teams to optimize solutions. These skills are crucial for designing ultra-fast, reliable trading systems that give firms a competitive edge in financial markets.

What are the typical challenges faced when working as an FPGA engineer in low latency trading environments?

FPGA engineers in low latency trading often face challenges such as optimizing hardware designs to achieve ultra-low latencies, integrating with rapidly changing software stacks, and ensuring reliable operation under extreme market conditions. The role requires balancing speed with accuracy, as even nanoseconds can impact trading outcomes. Collaboration with traders, software developers, and network engineers is essential to align hardware solutions with trading strategies and system requirements.

What is the difference between Fpga Low Latency Trading vs Fpga Algorithm Developer?

AspectFpga Low Latency TradingFpga Algorithm Developer
CredentialsHardware design, FPGA certifications, financial industry knowledgeHardware/software development, FPGA design, algorithm expertise
Work EnvironmentFinancial trading firms, high-frequency trading environmentsTech companies, financial institutions, R&D labs
Industry UsagePrimarily in trading and finance sectorsBroader tech sectors, including finance, telecom, and defense

While both roles involve FPGA development, Fpga Low Latency Trading focuses on optimizing hardware for ultra-fast trading systems, whereas Fpga Algorithm Developer designs and implements algorithms on FPGA platforms across various industries.

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Fpga Low Latency Trading jobs near you
Infographic showing various Fpga Low Latency Trading job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 16% Part Time, 4% Contract, and 1% Nights. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $147,056 per year, or $70.7 per hour.

Director of eSoftware Engineering - FPGA / Equities Low Latency Trading

JP Morgan Chase

Jersey City, NJ • On-site

$142K - $182K/yr

Full-time

Medical, Retirement

Re-posted 11 days ago

JPMorgan Chase & Co. rating

8.0

Company rating: 8.0 out of 10

Based on 499 frontline employees who took The Breakroom Quiz

72nd of 174 rated banks

Job description

If you are a software engineering leader ready to take the reins and drive impact, we've got an opportunity just for you.

As a Director of eSoftware Engineering at JPMorgan Chase within the Equities Electronic Trading team, you will set technical direction and personally contribute to the design and delivery of ultra-low latency market infrastructure used in equities electronic trading. You will build ultra-low latency pipelines spanning market data ingest, processing, and distribution as well as trading and execution workflows, with rigorous verification and production-grade operational controls. This role requires deep networking expertise (including TCP/IP), experience with Layer 1 switching and low-latency connectivity (including microwave), and the ability to take large programs from requirements through delivery, coordinating with internal compute and networking service organizations and managing outside vendors. This is a technical leadership role; will guide the team through architecture, design reviews, and execution. A core priority of this role is to advance the team's adoption of AI-assisted and spec-driven FPGA development and verification workflows, including executable specifications, automated review, and traceability from spec to silicon, with examples such as AI-assisted RTL and testbench generation to improve quality, throughput, and time-to-market.

Job responsibilities

  • Architect, implement, and optimize ultra-low latency FPGA-based pipelines for market data ingest, processing, and distribution as well as trading workflows, with a focus on determinism, measurement discipline, and production readiness.
  • Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and complementary protocol support (UDP, IP, multicast, ARP), time synchronization (PTP), and loss/latency instrumentation suitable for production operations.
  • Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
  • Partner with network engineering teams and external vendors to design, validate, and operate low-latency connectivity solutions, including microwave / wireless links, with clear operational runbooks and measurable service-level objectives.
  • Own verification strategy and execution, building robust testbenches in Python/Cocotb to achieve high functional coverage, strong regression quality, and fast debug cycles.
  • Drive timing closure and performance predictability, including floorplanning, static timing analysis, CDC/RDC correctness, power optimization, and post-route validation under realistic traffic and corner conditions.
  • Serve as technical lead for a team hardware and software engineers across the program lifecycle, taking large programs from requirements through production rollout while coordinating with internal compute and networking service organizations and managing outside vendors.
  • Lead the team's adoption and scaling of AI-assisted and spec-driven workflows for FPGA development and verification, including executable specifications, spec-to-implementation traceability, AI-assisted RTL generation and refactoring, automated code review, testbench and stimulus generation, bug triage, and performance tuning, with appropriate controls for correctness, IP protection, confidentiality, and auditability.

Required qualifications, capabilities, and skills

  • Formal training or certification on software engineering concepts and 10+ years applied experience. In addition, 5+ years of experience leading technologists to manage, anticipate and solve complex technical items within your domain of expertise and more broadly across the organization
  • Strong expertise and hands-on FPGA development experience in low-latency electronic trading and HFT systems.
  • Demonstrated expertise building ultra-low latency FPGA pipelines, including end-to-end performance measurement, deterministic design techniques, and latency/throughput trade-offs.
  • Advanced verification capability using Python and Cocotb, including functional coverage, constrained/random strategies as appropriate, regression automation, and debug discipline; familiarity with SystemVerilog and UVM as complementary verification approaches.
  • Strong market data domain knowledge across ingest, processing, and distribution in production trading environments.
  • Deep understanding of networking with proven implementation and troubleshooting experience in TCP, and strong competence across UDP, IP, multicast, ARP, and PTP, including packet parsing, buffering, congestion/flow considerations, and timestamping.
  • Experience with Layer 1 switching and ultra-low latency signal distribution concepts, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
  • Hands-on experience with microwave / wireless low-latency connectivity for market access, including latency budgeting, availability and environmental considerations, link engineering trade-offs, integration with FPGA-based termination/processing, and direct collaboration with specialist vendors and carriers.

Preferred qualifications, capabilities, and skills

  • Expertise with leading FPGA vendor toolchains and devices, including high-speed transceivers and high-speed Ethernet MAC/PCS integration.
  • Host/FPGA integration experience, including PCIe, DMA, AXI, driver/firmware interfaces, and performance profiling across the full stack.
  • Familiarity with exchange connectivity protocols, including production considerations for resiliency and change management.
  • Experience with, or strong interest in, AI-assisted and spec-driven approaches to FPGA development and verification, including executable specifications, AI-assisted RTL generation and refactoring, testbench and stimulus generation, automated code review, bug triage, and performance tuning, applied with appropriate guardrails for correctness, IP protection, confidentiality, and reproducibility. The successful candidate will help build and scale this capability within the team over time; deep prior expertise is not required at hire.


 

JPMorganChase, one of the oldest financial institutions, offers innovative financial solutions to millions of consumers, small businesses and many of the world's most prominent corporate, institutional and government clients under the J.P. Morgan and Chase brands. Our history spans over 200 years and today we are a leader in investment banking, consumer and small business banking, commercial banking, financial transaction processing and asset management.

We offer a competitive total rewards package including base salary determined based on the role, experience, skill set and location. Those in eligible roles may receive commission-based pay and/or discretionary incentive compensation, paid in the form of cash and/or forfeitable equity, awarded in recognition of individual achievements and contributions. We also offer a range of benefits and programs to meet employee needs, based on eligibility. These benefits include comprehensive health care coverage, on-site health and wellness centers, a retirement savings plan, backup childcare, tuition reimbursement, mental health support, financial coaching and more. Additional details about total compensation and benefits will be provided during the hiring process. 

We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants' and employees' religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation.

JPMorgan Chase & Co. is an Equal Opportunity Employer, including Disability/Veterans

J.P. Morgan's Commercial & Investment Bank is a global leader across banking, markets, securities services and payments. Corporations, governments and institutions throughout the world entrust us with their business in more than 100 countries. The Commercial & Investment Bank provides strategic advice, raises capital, manages risk and extends liquidity in markets around the world. 

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