Entry Level Pcb Layout Engineer Jobs in Oregon (NOW HIRING)

Qualifications:

• Associate's degree in Computer Drafting and Design, a similar course, or on-the-job experience.
• Experience in building systems mechanical design in semiconductor or related high-tech type facilities.

Preferred Additional Qualifications:

• Experience with 3D modeling and clash detection tools
• Knowledge of semiconductor tool requirements and installation processes
• Familiarity with safety and regulatory standards in high-tech manufacturing

Skills:

• Has deep knowledge of Revit, Navisworks, AutoCAD, Bluebeam, and other modeling and drafting programs necessary in the performance of the work required.
• Proven track record of precise drawing and model input.
• Demonstrated ability to take verbal direction and move project production forward with minimal supervision.
• Has a solid understanding of how your work affects the schedule.
• Ability to determine the correct path forward by asking pertinent questions and requesting clarity.
• Actively pursues knowledge of the focus subject area.
• Maintains a positive attitude and outlook.
• Demonstrates working knowledge of drawing and model input.
• Ability to break assignments down into required tasks, assign hours to each task, and provide work estimates to leadership on an as-needed basis.
• Has thorough understanding of drafting and modeling standards and requirements.

Responsibilities:

• Develop detailed layout designs for semiconductor equipment installations within fab and cleanroom environments
• Coordinate space planning, tool placement, and workflow optimization to maximize efficiency and throughput
• Collaborate with facilities, process, equipment, and construction teams to align layout designs with operational requirements
• Ensure compliance with cleanroom standards, safety regulations, and facility constraints (e.g., utilities, structural, and environmental)
• Produce and maintain layout drawings, 3D models, and installation documentation
• Support tool move-in, installation planning, and ramp-up activities
• Identify and resolve layout conflicts, including utility routing, clearance issues, and access requirements
• Contribute to continuous improvement of layout standards and best practices

In addition to the responsibilities of entry-level designers, intermediate-level designers are responsible for production speed, drawing, and model input as directed by more senior designers and engineers. Backchecking of your work to ensure a high level of accuracy is key in operating at this level. It is the responsibility of the intermediate-level designer to listen to and follow direction, take notes, self-motivate, be available and reliable, continue learning, and always push to meet deadlines. At this level, making the attempt to try new things is your responsibility and is expected.

General Tasks Performed:

• Creates and modifies drawings and models via conversations, redlines, and markups to a high degree of accuracy.
• Actively participates in department and project meetings.
• Prepares deliverables for all phases of the project including models, plans, elevations, sections, schedules, and details to support design and architectural leads for meetings, proposals, and construction documents.
• Readily displays Revit and / or Navisworks models during meetings. Performs model walk throughs as directed by more senior staff during presentations and coordination meetings.
• Provides status updates on drawing and model inputs. Estimates hours to complete given assignments.
• Coordinates designs and deliverables and resolves conflicts with / between all disciplines and existing field conditions where required.
• Assists in field survey of existing conditions.
• Responds to design and coordination requests, conflict resolution requests, and information sharing requests in a timely manner.
• Identifies incomplete work or gaps in own work and addresses them prior to review.

Comments/Special Instructions

• This req is targeting a JP2 or JP3 candidate. Please only submit candidates at the top of the range if they are more a high-level JP2 or JP3