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Entry Level Ic Layout Mask Designer Jobs (NOW HIRING)

Join Intel's groundbreaking quantum computing team as a Qubit Control IC Designer, where you'll ... Experience with silicon prototyping flow (design, validation, layout, tape-out, testing)

Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout ... at an IC level. Familiarity with various RF transceiver architectures and their trade-offs.

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Entry Level Ic Layout Mask Designer information

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How much do entry level ic layout mask designer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for entry level ic layout mask designer in the United States is $175,000.00, according to ZipRecruiter salary data. Most workers in this role earn between $162,500.00 and $187,500.00 per year, depending on experience, location, and employer.

What does an Entry Level IC Layout Mask Designer do?

An Entry Level IC Layout Mask Designer is responsible for creating the physical layouts of integrated circuits (ICs) based on schematic diagrams and design rules. They use specialized software to design the mask patterns that will be used in semiconductor manufacturing. Their work ensures that the final chip meets functional, performance, and manufacturing requirements. They collaborate closely with circuit designers and verification engineers to optimize layouts and resolve design issues. This role is often a starting point for a career in IC design and fabrication.

What are the key skills and qualifications needed to thrive as an Entry Level IC Layout Mask Designer, and why are they important?

To thrive as an Entry Level IC Layout Mask Designer, you need a solid understanding of semiconductor physics, circuit design fundamentals, and a relevant degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso or Mentor Graphics, and knowledge of design rules and verification processes, are typically required. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with engineers and ensuring design accuracy. These competencies are essential for producing high-quality, manufacturable integrated circuit layouts that meet stringent specifications and project timelines.

What are some typical challenges faced by entry-level IC layout mask designers, and how can they overcome them?

Entry-level IC layout mask designers often encounter challenges such as mastering complex design software, understanding stringent design rules, and collaborating with cross-functional teams. Adjusting to the fast pace of project cycles and ensuring accuracy in layout to meet manufacturing requirements can also be demanding. To overcome these challenges, new designers should seek mentorship from experienced colleagues, actively participate in team meetings to clarify requirements, and practice using industry-standard EDA tools to build confidence and proficiency.

What is the difference between Entry Level Ic Layout Mask Designer vs Entry Level Semiconductor Process Engineer?

AspectEntry Level Ic Layout Mask DesignerEntry Level Semiconductor Process Engineer
CredentialsAssociate's or Bachelor's in Electrical Engineering, MicroelectronicsAssociate's or Bachelor's in Chemical, Materials, or Electrical Engineering
Work EnvironmentDesign labs, cleanrooms, CAD softwareManufacturing facilities, labs, process development
Industry UsageSemiconductor fabrication, chip designSemiconductor manufacturing, process optimization
Common Search/ComparisonDesign-focused, layout, mask creationProcess-focused, fabrication, process steps

The Entry Level Ic Layout Mask Designer primarily focuses on creating detailed mask layouts for semiconductor chips using CAD tools, working closely with design teams. In contrast, the Entry Level Semiconductor Process Engineer concentrates on developing and optimizing manufacturing processes. While both roles require a background in electrical or materials engineering and involve working in semiconductor environments, their core responsibilities differ—design versus process development.

What cities are hiring for Entry Level Ic Layout Mask Designer jobs? Cities with the most Entry Level Ic Layout Mask Designer job openings:
What are the most commonly searched types of Ic Layout Mask Designer jobs? The most popular types of Ic Layout Mask Designer jobs are:
What states have the most Entry Level Ic Layout Mask Designer jobs? States with the most job openings for Entry Level Ic Layout Mask Designer jobs include:
Qubit Control IC Designer

Qubit Control IC Designer

Intel

On-site

Full-time

Medical, Retirement, PTO

Posted 5 days ago


Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

8th of 139 rated electronics manufacturers


Job description

Job Details:Job Description: 

Are you ready to be at the forefront of the quantum computing revolution? Join Intel's groundbreaking quantum computing team as a Qubit Control IC Designer, where you'll help shape the future of computing technology. This is an extraordinary opportunity to work on one of the most exciting and challenging frontiers in technology, designing the critical control electronics that will power Intel's quantum computers and potentially transform how we solve the world's most complex problems.

Why Join Us?This is your chance to be part of a revolutionary technology that will define the future of computing. You'll work with world-class engineers, access cutting-edge Intel technologies, and contribute to breakthroughs that could solve problems previously thought impossible. Join us in building the quantum computers of tomorrow!

Job Summary:In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of building the control electronics for Intel quantum computers. The team is focused on leveraging the latest Intel CMOS processes, packaging, and integration technologies to develop novel qubit control architectures and circuits that can scale to millions of qubits. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing.

Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey!

Key Responsibilities:

System Architecture and Design:

  • Architect, design, and test complex mixed-signal system-on-chip (SoC) and FPGA solutions that interface the microinstruction layer of the quantum computing stack to actual qubits

  • Generate complex control signals required to drive and read qubit states with precision and reliability

Signal Integrity Excellence:

  • Perform signal integrity analysis and optimization for qubit chips to ensure optimal performance

  • Apply electromagnetic (EM) modeling and simulation tools for signal integrity and crosstalk analysis

Collaborative Innovation:

  • Work in close collaboration with both software/algorithms and qubit development teams to create integrated solutions

  • Bridge the gap between quantum physics and practical electronic implementation

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous job and/or research experience.

Minimum Qualifications:

  • Bachelor's degree with 4 years of experience, or Master's with 3 years of experience or PhD degree with 1 year of experience in Electrical Engineering or related engineering field

  • Experience with RF/analog/mixed-signal circuit tape-out completed in an advanced process technology and lab testing

  • Experience with silicon prototyping flow (design, validation, layout, tape-out, testing)

  • Experience with architecture, design, implementation, and verification of mixed-signal systems including circuit blocks such as LNAs, Mixers, PAs, PLLs, VCOs, ADCs, DACs

  • Experience with electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on-chip/on-package interconnect

Preferred Qualifications:

  • Experience in high-level system design and validation with behavioral models (e.g., Matlab, Verilog, Veriloga, System Verilog, etc.)

  • Expertise with DSP/signal processing skills

  • Experience with quantum computing

  • Expertise for qubit design, fabrication, and control (preferred focus on spin qubits)

  • Hands-on experience with qubit characterization and control with dilution refrigerators and room lab-grade control electronics

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Massachusetts, Beaver BrookBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968