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Entry Level Ic Layout Mask Designer Jobs in Bothell, WA

Oxford Ionics

Senior QPU Design Engineer

Bothell, WA · On-site

$126K - $240K/yr

... designs for ion trapping chips into production. You will play an important part in shaping the ... At least 3 years of industry experience leading complex chip design and in IC layout. * A degree in ...

Oxford Ionics

Senior QPU Design Engineer

Bothell, WA · On-site

$126K - $240K/yr

... designs for ion trapping chips into production. You will play an important part in shaping the ... At least 3 years of industry experience leading complex chip design and in IC layout. * A degree in ...

Oxford Ionics

Senior QPU Design Engineer

Bothell, WA · On-site

$126K - $240K/yr

... designs for ion trapping chips into production. You will play an important part in shaping the ... At least 3 years of industry experience leading complex chip design and in IC layout. * A degree in ...

SpaceX

Entry Level Production Technician - PCBA

Redmond, WA · On-site

$29.50 - $37/hr

SMT placement, reflow, paste printing, conformal coating, masking, epoxy application, coating ... Ability to read, interpret, and work from layout drawings, mechanical drawings, assembly procedures ...

SpaceX

Assembly Technician - Entry Level

Redmond, WA

$29.50 - $37/hr

Support conformal coating, masking, epoxy application, and related processes. * Conduct functional ... Ability to read, interpret, and work from layout drawings, mechanical drawings, assembly procedures ...

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Entry Level Ic Layout Mask Designer information

See Bothell, WA salary details

$167.7K

$195.6K

$220.2K

How much do entry level ic layout mask designer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for entry level ic layout mask designer in Bothell, WA is $195,630.00, according to ZipRecruiter salary data. Most workers in this role earn between $181,700.00 and $209,600.00 per year, depending on experience, location, and employer.

What does an Entry Level IC Layout Mask Designer do?

An Entry Level IC Layout Mask Designer is responsible for creating the physical layouts of integrated circuits (ICs) based on schematic diagrams and design rules. They use specialized software to design the mask patterns that will be used in semiconductor manufacturing. Their work ensures that the final chip meets functional, performance, and manufacturing requirements. They collaborate closely with circuit designers and verification engineers to optimize layouts and resolve design issues. This role is often a starting point for a career in IC design and fabrication.

What are the key skills and qualifications needed to thrive as an Entry Level IC Layout Mask Designer, and why are they important?

To thrive as an Entry Level IC Layout Mask Designer, you need a solid understanding of semiconductor physics, circuit design fundamentals, and a relevant degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso or Mentor Graphics, and knowledge of design rules and verification processes, are typically required. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with engineers and ensuring design accuracy. These competencies are essential for producing high-quality, manufacturable integrated circuit layouts that meet stringent specifications and project timelines.

What are some typical challenges faced by entry-level IC layout mask designers, and how can they overcome them?

Entry-level IC layout mask designers often encounter challenges such as mastering complex design software, understanding stringent design rules, and collaborating with cross-functional teams. Adjusting to the fast pace of project cycles and ensuring accuracy in layout to meet manufacturing requirements can also be demanding. To overcome these challenges, new designers should seek mentorship from experienced colleagues, actively participate in team meetings to clarify requirements, and practice using industry-standard EDA tools to build confidence and proficiency.

What is the difference between Entry Level Ic Layout Mask Designer vs Entry Level Semiconductor Process Engineer?

AspectEntry Level Ic Layout Mask DesignerEntry Level Semiconductor Process Engineer
CredentialsAssociate's or Bachelor's in Electrical Engineering, MicroelectronicsAssociate's or Bachelor's in Chemical, Materials, or Electrical Engineering
Work EnvironmentDesign labs, cleanrooms, CAD softwareManufacturing facilities, labs, process development
Industry UsageSemiconductor fabrication, chip designSemiconductor manufacturing, process optimization
Common Search/ComparisonDesign-focused, layout, mask creationProcess-focused, fabrication, process steps

The Entry Level Ic Layout Mask Designer primarily focuses on creating detailed mask layouts for semiconductor chips using CAD tools, working closely with design teams. In contrast, the Entry Level Semiconductor Process Engineer concentrates on developing and optimizing manufacturing processes. While both roles require a background in electrical or materials engineering and involve working in semiconductor environments, their core responsibilities differ—design versus process development.

What cities near Bothell, WA are hiring for Entry Level Ic Layout Mask Designer jobs? Cities near Bothell, WA with the most Entry Level Ic Layout Mask Designer job openings:
Entry Level Ic Layout Mask Designer jobs near you

Senior QPU Design Engineer

Oxford Ionics

Bothell, WA • On-site

$126K - $240K/yr

Full-time

Medical, Dental, PTO

Posted 16 hours ago

Job description

Quantum is now, and it's built here.

Oxford Ionics, now part of IonQ, is pioneering the next generation of quantum computing. Using our world-leading trapped-ion technology, we're building the most powerful, accurate and reliable quantum systems to tackle problems that today's supercomputers cannot solve.

Joining Oxford Ionics means becoming part of a global IonQ team that is transforming the future of quantum technology - faster, at scale, and with real world impact.

What to expect:

We are looking for a Senior QPU Design Engineer to join our Processor Design team at Oxford Ionics/IonQ. In this role, you will be responsible for integrating all the features required for the successful operation of our quantum computers into complex chips. You will be directly contributing to the team's mission of advancing the design of high-performance quantum processing units, the novel technology that sits at the very heart of our quantum computers. You will work closely with scientists and fabrication engineers, understanding how the various parts of a chip influence and constrain each other, to bring new designs for ion trapping chips into production.

You will play an important part in shaping the hardware that supports our work in building the world's most advanced quantum systems.

What you'll be responsible for:

In this position, your primary responsibility will focus on turning operational requirements into chip layout, supporting the effective delivery of devices that enable the use of new technologies. You will have the opportunity to expand the range of features supported by our chips, contributing directly to the success of building utility-scale quantum computers.

Key responsibilities include: 

  • Guiding the end to end chip design process, from requirements to layout and tape-out.
  • Coordinating with other teams to ensure feasibility and compatibility between the various layers of the chip.
  • Collaborating with scientists to discuss their requirements and settle on specifications.
  • Laying out complex multi-layer chips, including metal track routing and interfaces with photonics and CMOS.

Requirements

To be successful in this role, you will need prior hands-on experience in chip layout, specifically translating design requirements into feature, as well as taking on layout work. We are looking for someone who can work cross-functionally to define various aspects of chip design, contributing effectively within a fast moving, highly technical team. You will need to be able to take charge of projects independently, solve problems along the way and drive the design process while taking responsibility for delivery of the final tape-out.

You'd be a great fit with:

  • At least 3 years of industry experience leading complex chip design and in IC layout.
  • A degree in engineering, electronics or science, or equivalent industry experience in a technical or scientific environment.
  • Proven ability to consult and coordinate between multiple stakeholders.
  • Strong collaboration and communication skills.

Additional experience that may be beneficial includes experience in scripted generation of layout (GSDFactory in Python or similar), using Cadence for IC layout, and experience in ion trap and/or photonics design or IC packaging.

Benefits

Be part of a team that's shaping the future of quantum. We offer more than just a role, you'll join a world class community of scientists, engineers and innovators working to unlock the full potential of quantum computing.

We offer a range of benefits, including opportunities to further your career alongside industry leaders, a competitive salary with IonQ stock options, an annual performance bonus, generous annual leave, flexible hybrid working, private medical and dental insurance for you and your family, and much more.

Join us and be part of the future of quantum computing.

We're proud to be an equal opportunity employer and welcome applicants from all backgrounds.

US Salary Bandings:

$126,800 - $240,600

Apply