2

Entry Level Ic Layout Mask Designer Jobs in Bothell, WA

Painter Apprentice

Seattle, WA · On-site

$18.25 - $22.75/hr

The Painter Apprentice is an entry-level position designed for individuals who want to start a ... Learning & Support * Assist experienced painters with surface prep, masking, caulking, sanding, and ...

Showing results 21-38

Entry Level Ic Layout Mask Designer information

See Bothell, WA salary details

$167.7K

$195.6K

$220.2K

How much do entry level ic layout mask designer jobs pay per year?

As of Sep 4, 2026, the average yearly pay for entry level ic layout mask designer in Bothell, WA is $195,630.00, according to ZipRecruiter salary data. Most workers in this role earn between $181,700.00 and $209,600.00 per year, depending on experience, location, and employer.

What does an entry level IC layout mask designer do?

An Entry Level IC Layout Mask Designer is responsible for creating the physical layouts of integrated circuits (ICs) based on schematic diagrams and design rules. They use specialized software to design the mask patterns that will be used in semiconductor manufacturing. Their work ensures that the final chip meets functional, performance, and manufacturing requirements. They collaborate closely with circuit designers and verification engineers to optimize layouts and resolve design issues. This role is often a starting point for a career in IC design and fabrication.

What are the key skills and qualifications needed to thrive as an entry level IC layout mask designer?

To thrive as an Entry Level IC Layout Mask Designer, you need a solid understanding of semiconductor physics, circuit design fundamentals, and a relevant degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso or Mentor Graphics, and knowledge of design rules and verification processes, are typically required. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with engineers and ensuring design accuracy. These competencies are essential for producing high-quality, manufacturable integrated circuit layouts that meet stringent specifications and project timelines.

What are some typical challenges faced by entry level IC layout mask designers, and how can they overcome them?

Entry-level IC layout mask designers often encounter challenges such as mastering complex design software, understanding stringent design rules, and collaborating with cross-functional teams. Adjusting to the fast pace of project cycles and ensuring accuracy in layout to meet manufacturing requirements can also be demanding. To overcome these challenges, new designers should seek mentorship from experienced colleagues, actively participate in team meetings to clarify requirements, and practice using industry-standard EDA tools to build confidence and proficiency.

What is the difference between Entry Level Ic Layout Mask Designer vs Entry Level Semiconductor Process Engineer?

AspectEntry Level Ic Layout Mask DesignerEntry Level Semiconductor Process Engineer
CredentialsAssociate's or Bachelor's in Electrical Engineering, MicroelectronicsAssociate's or Bachelor's in Chemical, Materials, or Electrical Engineering
Work EnvironmentDesign labs, cleanrooms, CAD softwareManufacturing facilities, labs, process development
Industry UsageSemiconductor fabrication, chip designSemiconductor manufacturing, process optimization
Common Search/ComparisonDesign-focused, layout, mask creationProcess-focused, fabrication, process steps

The Entry Level Ic Layout Mask Designer primarily focuses on creating detailed mask layouts for semiconductor chips using CAD tools, working closely with design teams. In contrast, the Entry Level Semiconductor Process Engineer concentrates on developing and optimizing manufacturing processes. While both roles require a background in electrical or materials engineering and involve working in semiconductor environments, their core responsibilities differ—design versus process development.

What cities near Bothell, WA are hiring for Entry Level Ic Layout Mask Designer jobs?

Cities near Bothell, WA with the most Entry Level Ic Layout Mask Designer job openings:

Infographic showing various Entry Level Ic Layout Mask Designer job openings in Bothell, WA as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $195,630 per year, or $94.1 per hour.

New Graduate Engineer, Silicon Engineering

SpaceX

Redmond, WA • On-site

$145K - $200K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 20 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 151 frontline employees who took The Breakroom Quiz

16th of 72 rated aerospace companies


Job description

NEW GRADUATE ENGINEER, SILICON ENGINEERING

Are you an engineering student graduating in fall or this upcoming spring/summer that is looking for full-time employment after graduation? We are looking for engineers to help us develop next generation silicon for SpaceX. The team is hiring engineers from pre-silicon through post-silicon across many disciplines in RF/Analog IC, RTL design, design verification, physical design, DFT, validation and more using state-of-the-art tools and methodologies. The ideal candidate will be a hands-on self-starter who can execute the steps required to fully design and verify complex designs.

Full-time employment is available working on our Starlink program in Palo Alto (CA), Irvine (CA), or Redmond (WA). 

RESPONSIBILITIES:

  • ASIC/FPGA Design & Verification
    • Participate in all phases of ASIC/FPGA design and verification flows
    • Contribute towards design architecture, RTL implementation and/or verification, and emulation
    • Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python)
    • Hands-on self-starter who can execute the steps required to fully verify a complex digital design
  • RF/Analog IC Design
    • Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains
    • Derive specifications for the RFIC subsystems and circuits
    • Develop RF/microwave circuits in state-of-the-art SiGe or CMOS processes
    • Perform IC floor planning and layout
  • Digital Signal Processing
    • Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
    • Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
  • Physical Design
    • Perform synthesis and physical implementation steps (synthesis, floor planning, place and route, timing/noise analysis, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
    • Develop/improve physical design methodologies and automation scripts for various implementation steps
    • Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs

BASIC QUALIFICATIONS:

  • Graduating with a bachelor's degree, master's degree or PhD in 2026 or 2027
  • Bachelor's degree in an engineering discipline, mathematics or physics
  • Experience working with ASIC, SOC, FPGA, RFIC, or MMIC

PREFERRED SKILLS AND EXPERIENCE:

  • Understanding of computer architecture
  • Experience in one or more of the following areas:
    • Analog or digital CMOS integrated circuit design and/or physical design
    • SystemVerilog, Verilog, VHDL or C/C++
    • Scripting languages, e.g. Python for automation
    • Object-oriented programming
    • Simulation tools such as ADS, Spectre, HFSS or Momentum
    • RTL design, chip bring-up, verification, and/or post-silicon validation experience
    • Digital signal processing

ADDITIONAL REQUIREMENTS: 

  • Ability to work extended hours and weekends as necessary to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay Range:
Level 1: $125,000.00 - $165,000.00
Level 2: $145,000.00 - $200,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees in Washington State accrue paid sick time in compliance with state and federal law. Company shuttles are offered to employees for roundtrip travel from select Seattle locations to the SpaceX Redmond office Monday to Friday.


What SpaceX employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


SpaceX logo

About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US