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Entry Level Ic Layout Designer Jobs (NOW HIRING)

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power ...

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

  • Medical

  • Dental

  • Retirement

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

  • Medical

  • Dental

  • Retirement

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

  • Medical

  • Dental

  • Retirement

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power ...

Heico

Entry Level PCB Designer

Camarillo, CA

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Entry Level PCB Designer's role will be responsible for executing PCB designs that meet ... Apply RF layout techniques including isolation, via stitching, and shielding strategies * Support ...

HEICO

Entry Level PCB Designer

Camarillo, CA

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Entry Level PCB Designer's role will be responsible for executing PCB designs that meet ... Apply RF layout techniques including isolation, via stitching, and shielding strategies * Support ...

HEICO

Entry Level PCB Designer

Camarillo, CA · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Entry Level PCB Designer's role will be responsible for executing PCB designs that meet ... Apply RF layout techniques including isolation, via stitching, and shielding strategies * Support ...

Heico

Entry Level PCB Designer

Camarillo, CA · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Entry Level PCB Designer's role will be responsible for executing PCB designs that meet ... Apply RF layout techniques including isolation, via stitching, and shielding strategies * Support ...

Heico

Entry Level PCB Designer-Camarillo,California

Malibu, CA · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Entry Level PCB Designer's role will be responsible for executing PCB designs that meet ... Apply RF layout techniques including isolation, via stitching, and shielding strategies * Support ...

Wander.com, Inc.

Entry Level Graphic Designer

Austin, TX · On-site

$45K/yr

About the role Wander is looking for an entry-level Graphic Designer to join our team in Austin ... Genuine interest in graphic design, layout, typography, and visual branding, with an eye for luxury ...

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Entry Level Ic Layout Designer information

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How much do entry level ic layout designer jobs pay per hour?

As of Aug 17, 2026, the average hourly pay for entry level ic layout designer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What does an entry level IC layout designer do?

An Entry Level IC Layout Designer is responsible for creating the physical layout of integrated circuits (ICs) based on circuit schematics and design rules. They use specialized software tools to position transistors, wires, and other components on silicon chips, ensuring that the design meets performance, area, and manufacturing requirements. This role often involves collaborating with circuit designers and verification engineers to optimize layouts for efficiency and manufacturability. Entry level designers typically work under the supervision of more experienced engineers and gain hands-on experience with industry-standard EDA tools. Over time, they develop a deeper understanding of IC design principles and fabrication processes.

What are the key skills and qualifications needed to thrive as an entry level IC layout designer?

To thrive as an Entry Level IC Layout Designer, you need a solid understanding of semiconductor fundamentals, circuit design basics, and a relevant degree in electrical engineering or a related field. Proficiency in CAD tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, along with familiarity with design rule checking (DRC) and layout versus schematic (LVS) verification, is typically required. Strong attention to detail, effective communication, and the ability to collaborate within engineering teams are standout soft skills. These skills ensure accurate and efficient IC layouts, compliance with manufacturing constraints, and smooth teamwork throughout the design process.

What are some common challenges faced by entry level IC layout designers, and how can they overcome them?

Entry-level IC layout designers often encounter challenges such as understanding complex design rules, adapting to new EDA (Electronic Design Automation) tools, and ensuring layouts meet both electrical and manufacturing constraints. Collaborating closely with senior designers and verification engineers is essential to resolve issues quickly and learn best practices. It’s helpful to proactively seek feedback, participate in team reviews, and continuously practice with layout tools to build confidence and expertise in this highly detail-oriented role.
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Entry Level Ic Layout Designer jobs near you
Infographic showing various Entry Level Ic Layout Designer job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 81% Full Time, 13% Part Time, 2% Contract, and 3% Nights. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

Package Design & Layout Engineer

Cspeed

Palo Alto, CA • On-site

Full-time

Posted 12 days ago

Job description

The Role

You will own the physical design of our optical engine packages - redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on layout role with real architectural influence.

You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate vendor, OSAT). You will not be handed a finished floorplan to route - you will help define it.

What You'll Do

Layout execution

  • Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles, from floorplan through tape-out.
  • Define and release bump maps, ball maps, and escape routing strategies for multi-die assemblies (PIC, EIC, and light source die).
  • Design to 200G/lane-class electrical requirements: differential pair routing, reference-plane integrity, crosstalk isolation, and power delivery for high-current, low-noise rails.

Co-design and floor planning

  • Participate from concept phase: produce preliminary floorplans and stack-up proposals that reconcile electrical, optical, thermal, and mechanical constraints before they are frozen.
  • Iterate with SI/PI engineers on test routes to converge routing topologies and design rules.

Design rules, DFM, and supplier engagement

  • Work directly with wafer fabs, substrate suppliers, and OSATs to capture and negotiate design rules, stack-ups, and assembly constraints.
  • Generate fab and assembly release packages; drive DFM/DFA closure and design reviews through to sign-off.
  • Flag rule conflicts early and propose alternatives rather than routing around them silently.

Verification and automation

  • Run and own physical verification: DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board.
  • Manage netlists for heterogeneous assemblies across revisions and product variants.
  • Build scripted automation (SKILL, Python, or equivalent) for repetitive layout, checking, and release tasks.

Build support

  • Support test vehicle definition, first builds, bring-up, failure analysis, and yield learning - including layout changes driven by assembly reality.
Required Qualifications
  • BS or MS in Electrical Engineering, or equivalent practical background.
  • 6+ years of IC package physical design, including at least one product taken from concept through tape-out and volume-relevant build.
  • Expert-level proficiency in a package layout tool: Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC Package, or equivalent.
  • Demonstrated experience with multi die packaging: 2D or 2.5/3D integration.
  • Working fluency with multi-layer organic substrate construction and how material and stack-up choices constrain routing.
  • Practical experience closing DFM/DFA with external substrate suppliers and OSATs.
  • Comfortable working in English across a distributed team and multiple time zones.
Preferred Qualifications
  • Demonstrated experience with advanced packaging: 2.5D/3D integration, RDL, TSV interposers, fan-out, microbump or Cu-pillar flip-chip.
  • Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power integrity workflows (e.g. Cadence Sigrity/PowerSI, Ansys).
  • Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and AutoCAD file exchange.
  • Experience with package/IC co-design environments (e.g. Cadence Integrity 3D-IC).
  • Scripting for design automation and rule checking.
  • Experience at a startup or on a first-of-its-kind product, where the design rules did not exist yet.
Why This Role Is Different

Most package layout roles are a step in someone else's flow. Here, the package is the product. You will be one of a handful of people who determine whether a next-generation optical engine is manufacturable, and you will see your layout decisions land in silicon and in an OSAT line within months, not years.

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