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Entry Level Ic Layout Designer Jobs (NOW HIRING)

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...

Solvenow Inc.

Layout Designer

Portland, OR

Contribute to continuous improvement of layout standards and best practices In addition to the responsibilities of entry-level designers, intermediate-level designers are responsible for production ...

Micron

Senior Layout Designer - Pathfinding

Boise, ID · On-site

As a Senior Layout Designer, you will develop and prepare multi-dimensional layouts. You will ... IC layout design experience with NAND, DRAM, and/or SRAM * Programming skills and leveraging ...

Cirrus Logic

IC Layout Design

Greensboro, NC · On-site

Solving layout design issues and applying proactive intervention * Proactively work with design engineers to achieve efficient circuit performance * Design analog & mixed-signal layouts * Understand ...

Texas Instruments

Analog IC Design Engineer

Dallas, TX · On-site

Direct IC layout to ensure performance, reliability, and manufacturability * Characterize silicon ... We offer competitive pay and benefits designed to help you and your family live your best life.

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX · On-site

$123K/yr

Supervise IC layout of digital blocks to ensure timing, power, and signal integrity requirements ... We offer competitive pay and benefits designed to help you and your family live your best life.

Texas Instruments

Digital IC Design Engineer

Dallas, TX

$123K/yr

Supervise IC layout of digital blocks to ensure timing, power, and signal integrity requirements ... We offer competitive pay and benefits designed to help you and your family live your best life.

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

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Entry Level Ic Layout Designer information

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How much do entry level ic layout designer jobs pay per hour?

As of Aug 17, 2026, the average hourly pay for entry level ic layout designer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What does an entry level IC layout designer do?

An Entry Level IC Layout Designer is responsible for creating the physical layout of integrated circuits (ICs) based on circuit schematics and design rules. They use specialized software tools to position transistors, wires, and other components on silicon chips, ensuring that the design meets performance, area, and manufacturing requirements. This role often involves collaborating with circuit designers and verification engineers to optimize layouts for efficiency and manufacturability. Entry level designers typically work under the supervision of more experienced engineers and gain hands-on experience with industry-standard EDA tools. Over time, they develop a deeper understanding of IC design principles and fabrication processes.

What are the key skills and qualifications needed to thrive as an entry level IC layout designer?

To thrive as an Entry Level IC Layout Designer, you need a solid understanding of semiconductor fundamentals, circuit design basics, and a relevant degree in electrical engineering or a related field. Proficiency in CAD tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, along with familiarity with design rule checking (DRC) and layout versus schematic (LVS) verification, is typically required. Strong attention to detail, effective communication, and the ability to collaborate within engineering teams are standout soft skills. These skills ensure accurate and efficient IC layouts, compliance with manufacturing constraints, and smooth teamwork throughout the design process.

What are some common challenges faced by entry level IC layout designers, and how can they overcome them?

Entry-level IC layout designers often encounter challenges such as understanding complex design rules, adapting to new EDA (Electronic Design Automation) tools, and ensuring layouts meet both electrical and manufacturing constraints. Collaborating closely with senior designers and verification engineers is essential to resolve issues quickly and learn best practices. It’s helpful to proactively seek feedback, participate in team reviews, and continuously practice with layout tools to build confidence and expertise in this highly detail-oriented role.
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Entry Level Ic Layout Designer jobs near you
Infographic showing various Entry Level Ic Layout Designer job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 81% Full Time, 13% Part Time, 2% Contract, and 3% Nights. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA

Full-time

Re-posted 20 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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