CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$184K - $324K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
Entry Level Design Verification Engineer information
See Portland, OR salary details
$111.9K - $117.8K
0% of jobs
$117.8K - $123.7K
0% of jobs
$123.7K - $129.7K
0% of jobs
$129.7K - $135.6K
0% of jobs
$135.6K - $141.5K
0% of jobs
$143.8K is the 25th percentile. Wages below this are outliers.
$141.5K - $147.5K
65% of jobs
$147.5K - $153.4K
0% of jobs
$153.4K - $159.3K
0% of jobs
$159.3K - $165.2K
0% of jobs
$165.2K - $171.2K
0% of jobs
$172.8K is the 75th percentile. Wages above this are outliers.
$171.2K - $177.1K
35% of jobs
$111.9K
$158.2K
$177.1K
How much do entry level design verification engineer jobs pay per year?
As of Aug 6, 2026, the average yearly pay for entry level design verification engineer in Portland, OR is $158,174.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,200.00 and $176,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as an entry level design verification engineer?
To thrive as an Entry Level Design Verification Engineer, you need a solid understanding of digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering, computer engineering, or a related field. Familiarity with hardware description languages (such as Verilog or VHDL), simulation tools, and industry-standard verification frameworks is essential. Strong analytical skills, attention to detail, and effective communication are vital soft skills for diagnosing issues and collaborating with design teams. These skills ensure accurate verification of hardware designs and smooth integration within the broader engineering workflow.
What is an entry level design verification engineer?
An Entry Level Design Verification Engineer ensures that hardware designs function correctly before production. They write and run testbenches using languages like SystemVerilog and work with simulation tools to verify chip functionality. Their role involves debugging, analyzing test results, and collaborating with designers to refine designs. This position is crucial in the semiconductor industry to prevent costly design errors. Typically, they work with verification methodologies like UVM to create efficient and reusable test environments.
What does an entry level design verification engineer do?
As an Entry Level Design Verification Engineer, your daily activities often include writing and executing testbenches, analyzing simulation results, identifying design bugs, and collaborating closely with design and development engineers to resolve issues. You may also be responsible for maintaining verification documentation and participating in code reviews or team meetings. The role involves a mix of hands-on technical work and teamwork, allowing you to learn best practices from experienced colleagues. Over time, you'll have opportunities to take on more complex verification tasks and contribute to process improvements as you gain experience.
What are popular job titles related to Entry Level Design Verification Engineer jobs in Portland, OR? For Entry Level Design Verification Engineer jobs in Portland, OR, the most frequently searched job titles are:
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What job categories do people searching Entry Level Design Verification Engineer jobs in Portland, OR look for? The top searched job categories for Entry Level Design Verification Engineer jobs in Portland, OR are:
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$184K - $324K/yr
Full-time
Medical, Dental, Retirement
Re-posted yesterday
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
Description
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.
Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.
• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.
Preferred Qualifications
Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence
Understanding of deep sub-micron technologies and scaling trends
Working knowledge of CPU microarchitecture including common fundamental timing paths
Working knowledge of clock-domain crossing and reset-domain crossing
Experience with RTL modeling and assertion based verification is a plus
Possess data parsing, analysis and representation/plotting skills
Minimum Qualifications
Minimum BS and 10+ years of relevant experience
Experience with a static timing analysis tool such as PrimeTime® or Tempus®
Experience with timing analysis with multiple clock and power domains, noise analysis, and fixing noise in designs
Experience with variation modeling
Experience with TCL and either Perl or Python
Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
Description
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.
Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.
• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.
Preferred Qualifications
Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence
Understanding of deep sub-micron technologies and scaling trends
Working knowledge of CPU microarchitecture including common fundamental timing paths
Working knowledge of clock-domain crossing and reset-domain crossing
Experience with RTL modeling and assertion based verification is a plus
Possess data parsing, analysis and representation/plotting skills
Minimum Qualifications
Minimum BS and 10+ years of relevant experience
Experience with a static timing analysis tool such as PrimeTime® or Tempus®
Experience with timing analysis with multiple clock and power domains, noise analysis, and fixing noise in designs
Experience with variation modeling
Experience with TCL and either Perl or Python
Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976