Design Verification Engineer Startup Jobs in Arizona

To take technical lead or significant contribution of Analog design of complex power management integrated circuits. You will be expected to support analog team members with guidance in Analog best practice, drive identification and implementation of improvements, and will represent Dialog in front of external customers.

To take technical lead or significant contribution of Analog design of complex power management integrated circuits. You will be expected to support analog team members with guidance in Analog best practice, drive identification and implementation of improvements, and will represent Dialog in front of external customers.

• As a mixed signal verification engineer, you will be responsible for the verification and modeling of mixed-signal power chips, such as PMICs and battery chargers. You will work closely with cross-functional teams, including design, verification, and systems teams, to ensure the successful development and integration of mixed signal components in complex systems.
• Verification: Perform chip-level verification of analog and mixed-signal circuits using advanced simulation tools and methodologies.
• Modeling: Create and maintain accurate models of analog circuits using languages such as SystemVerilog and Verilog-AMS.
• Verification Plan Development: Develop comprehensive verification and modeling plans to ensure thorough verification of mixed-signal circuits and systems.
• Debugging: Identify and resolve issues in mixed-signal circuits, including debugging failing test cases and models, and addressing simulation slowdowns.
• Collaboration: Work closely with design and verification teams to ensure proper integration of analog and digital components.
• Documentation: Document verification plans and results to ensure clear communication and traceability.
• Customer interactions: Work and communicate effectively with the external customer to ensure verification needs are met.

• Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8-12+ years in mixed-signal verification, digital verification, modeling, power management, or related semiconductor development. Switching converter experience is a plus.
• Communication: Excellent communication and teamwork skills to collaborate effectively with cross-functional teams and the customer.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on worldleading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.