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Cpu Rtl Design Engineer Jobs in Chicago, IL (NOW HIRING)

Eliyan

Architecture - I/O Architect

Mundelein, IL

Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...

Apply Early

OceanComm, Inc.

Engineering Intern / Co-op

Chicago, IL · On-site

$35 - $55/hr

Experience with CAD / 3D printing * Familiarity with lab equipment (e.g. oscilloscopes, probes ... Experience with FPGA / RTL (e.g. SystemVerilog, UVM, cocotb) Benefits * Close mentorship and ...

Apply Early

OceanComm, Inc.

Engineering Intern / Co-op

Chicago, IL · On-site

$35 - $55/hr

Experience with CAD / 3D printing * Familiarity with lab equipment (e.g. oscilloscopes, probes ... Experience with FPGA / RTL (e.g. SystemVerilog, UVM, cocotb) Benefits * Close mentorship and ...

OceanComm, Inc.

Engineering Intern / Co-op

Chicago, IL · On-site

$35 - $55/hr

Experience with CAD / 3D printing * Familiarity with lab equipment (e.g. oscilloscopes, probes ... Experience with FPGA / RTL (e.g. SystemVerilog, UVM, cocotb) Benefits * Close mentorship and ...

Canonical

Telco Cloud Field Engineer

Chicago, IL · On-site +1

Design and implement telco-grade open source multi-tenant private clouds and micro clouds ... like CPU Pinning, NUMA, SR-IOV, DPDK, etc * Familiarity with telco architecture and industry ...

Kaav Inc.

Teradata Infrastructure DBA

Chicago, IL · On-site

Data distribution and primary index design; collecting statistics and understanding optimize ... One of them, View point is mandatory. • Capacity planning, trending, and forecasting for CPU ...

Kyndryl

Mainframe z/VM & Linux

Chicago, IL · On-site

Who We Are At Kyndryl, we design, build, manage and modernize the mission-critical technology ... The Role We are seeking an experienced Mainframe z/VM & Linux Engineer to support IBM Z ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Chicago, IL

Cpu Rtl Design Engineer information

See Chicago, IL salary details

$41.7K

$90.8K

$163.3K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 1, 2026, the average yearly pay for cpu rtl design engineer in Chicago, IL is $90,807.00, according to ZipRecruiter salary data. Most workers in this role earn between $70,000.00 and $101,500.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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What job categories do people searching Cpu Rtl Design Engineer jobs in Chicago, IL look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Chicago, IL are:
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Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Chicago, IL as of June 2026, with employment types broken down into 80% Full Time, 16% Part Time, 1% Temporary, and 3% Contract. Highlights an 90% Physical, 6% Hybrid, and 4% Remote job distribution, with an average salary of $90,807 per year, or $43.7 per hour.

Architecture - I/O Architect

Eliyan

Mundelein, IL

Full-time

Posted 13 days ago

Be an early applicant

Job description

Join the leading chiplet startup! As an Eliyan NuLink PHY IO Architect, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the definition and development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will own the architecture, oversee design and validation, and be a focal point for customer and marketing team interactions. You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits. ONSITE M-F
Key Responsibilities:
  • Architecture: Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach.
  • Protocol Design: Design protocol conversion layers with transaction ordering, credit-based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains 
  • Performance Evaluation and Optimization: Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity.  Conduct technical evaluation and benchmark analysis against internal and external IPs.
  • Collaboration: Partner with ASIC, firmware, and post-silicon teams. Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB).  Create clear and comprehensive architecture specifications with foolproof integration guidelines. 
  • Validation: Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance
  • Compliance: Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards.
  • Leadership: Mentor engineers on protocol implementation, timing constraints, and hierarchical design.  Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders.
 
Minimum Qualifications:
  • Expertise in multiple areas of architecture definition, chip micro-architecture, protocol definition and implementation
  • Strong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA
  • Strong scripting and automation skills
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • 8+ years' of experience
 
Ideal Qualifications:
  • 15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts
  • Performance modeling of hardware implementations with high level languages like C, C++ or SystemC
  • Adept at clocking and floorplan guidelines for PHY implementation
  • Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve productivity and power aware designs
  • Exceptional problem-solving skills.
 

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.