FPGA Engineer
Schaumburg, IL ยท On-site
$127K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Schaumburg, IL ยท On-site
$127K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Schaumburg, IL ยท On-site
$127K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Chicago, IL ยท On-site
$131K - $175K/yr
Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...
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Chicago, IL ยท On-site
$131K - $175K/yr
Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...
$131K - $175K/yr
Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...
$131K - $175K/yr
Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...
Cary, IL ยท On-site
$117K - $118K/yr
... Engineering to assure effective and efficient projectexecution Education and Experience * hands-on ... digital design from Architecture (schematics and RTL) to GDS * MSEE preferred Key competencies ...
Cary, IL ยท On-site
$117K - $118K/yr
... Engineering to assure effective and efficient projectexecution Education and Experience * hands-on ... digital design from Architecture (schematics and RTL) to GDS * MSEE preferred Key competencies ...
Chicago, IL ยท On-site
Design, develop, and execute performance, load, stress, spike, and endurance tests using Apache ... Response time * Throughput * CPU utilization * Memory utilization * Error rates * Good ...
Chicago, IL ยท On-site
Design, develop, and execute performance, load, stress, spike, and endurance tests using Apache ... Response time * Throughput * CPU utilization * Memory utilization * Error rates * Good ...
Chicago, IL ยท On-site
Design, develop, and execute performance, load, stress, spike, and endurance tests using Apache ... Response time * Throughput * CPU utilization * Memory utilization * Error rates * Good ...
Chicago, IL ยท On-site
Design, develop, and execute performance, load, stress, spike, and endurance tests using Apache ... Response time * Throughput * CPU utilization * Memory utilization * Error rates * Good ...
Chicago, IL ยท On-site
$150K - $250K/yr
Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ... Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing ...
Chicago, IL ยท On-site
$150K - $250K/yr
Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ... Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing ...
$50.50 - $65.50/hr
Experience with * Performance profiling (CPU/memory) * Load testing techniques * Distributed ... Data pipeline design * Familiarity with: * Terraform * Monitoring tools (Datadog, CloudWatch)
New
$50.50 - $65.50/hr
Experience with * Performance profiling (CPU/memory) * Load testing techniques * Distributed ... Data pipeline design * Familiarity with: * Terraform * Monitoring tools (Datadog, CloudWatch)
New
Experience with physical design tools (Cadence Innovus, Synopsys ICC2, Siemens Calibre) and RTL\u0002to-GDSII flows * Strong programming/scripting: Python, C/C++, Tcl, Shell (bash); Verilog/VHDL ...
Quick apply
Experience with physical design tools (Cadence Innovus, Synopsys ICC2, Siemens Calibre) and RTL\u0002to-GDSII flows * Strong programming/scripting: Python, C/C++, Tcl, Shell (bash); Verilog/VHDL ...
$128K - $169K/yr
... CPU cache optimization) to meet stringent SLAs. * Work closely with engineers and stakeholders ... GC tuning and GC-free design (ZGC, Shenandoah, off-heap allocation, object pooling) * Lock-free and ...
$128K - $169K/yr
... CPU cache optimization) to meet stringent SLAs. * Work closely with engineers and stakeholders ... GC tuning and GC-free design (ZGC, Shenandoah, off-heap allocation, object pooling) * Lock-free and ...
Cary, IL ยท On-site +1
$157K - $292K/yr
Leading customer engagements on standard cell library optimization and RTL->GDS enablement ... Performing design of experiments and running Genus/Innovus to validate techLEF correctness and ...
Cary, IL ยท On-site +1
$157K - $292K/yr
Leading customer engagements on standard cell library optimization and RTL->GDS enablement ... Performing design of experiments and running Genus/Innovus to validate techLEF correctness and ...
$127K - $167K/yr
The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...
$127K - $167K/yr
The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... RTL Experience with network capture and analysis tools (e.g., Wireshark, Corvil) and hardware ...
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... RTL Experience with network capture and analysis tools (e.g., Wireshark, Corvil) and hardware ...
Chicago, IL ยท On-site
$127K - $167K/yr
The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...
Quick apply
Chicago, IL ยท On-site
$127K - $167K/yr
The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...
Chicago, IL ยท On-site
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
Chicago, IL ยท On-site
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
Mundelein, IL ยท On-site
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
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Mundelein, IL ยท On-site
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
Collaborate closely with analog, digital RTL, and physical design teams to ensure algorithm-to ... D in Electrical Engineering, Computer Engineering, or related fields * 10+ years of experience in ...
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Collaborate closely with analog, digital RTL, and physical design teams to ensure algorithm-to ... D in Electrical Engineering, Computer Engineering, or related fields * 10+ years of experience in ...
Chicago, IL ยท Hybrid
$118K - $141K/yr
The Senior Staff Data Engineer will be proficient with data platform architecture, design, data ... CPU time/load timing. * Deeper Knowledge on Snowflake License model and their continuous data ...
Chicago, IL ยท Hybrid
$118K - $141K/yr
The Senior Staff Data Engineer will be proficient with data platform architecture, design, data ... CPU time/load timing. * Deeper Knowledge on Snowflake License model and their continuous data ...
Chicago, IL ยท On-site
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
Chicago, IL ยท On-site
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
You will design and build ultra-low-latency solutions, including high-performance APIs, kernel ... Familiarity with SystemVerilog or Verilog, including the ability to read and interpret RTL
$41.7K - $52.8K
2% of jobs
$52.8K - $63.8K
11% of jobs
$69.7K is the 25th percentile. Wages below this are outliers.
$63.8K - $74.9K
23% of jobs
The median wage is $82K / yr.
$74.9K - $85.9K
22% of jobs
$85.9K - $97K
17% of jobs
$97.3K is the 75th percentile. Wages above this are outliers.
$97K - $108K
9% of jobs
$108K - $119.1K
6% of jobs
$119.1K - $130.1K
3% of jobs
$130.1K - $141.2K
3% of jobs
$141.2K - $152.2K
2% of jobs
$152.2K - $163.3K
1% of jobs
$41.7K
$90.8K
$163.3K
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
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Guided missile and space vehicle manufacturing
11 - 50 Employees
Washington, DC, US
2013