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Cpu Rtl Design Engineer Jobs in Chicago, IL (NOW HIRING)

IMC

HPC Engineer

Chicago, IL

Partner with Researchers, Quants, and MLEs to analyze, optimize, and scale HPC workloads across CPU ... Work with platform teams to influence system design decisions based on real workload behavior and ...

EndoSec LLC

FPGA Engineer

Chicago, IL · On-site

$133K - $172K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

EndoSec LLC

FPGA Engineer

Schaumburg, IL · On-site

$127K - $164K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

IMC

HPC Engineer

Chicago, IL · On-site

$200K - $225K/yr

Partner with Researchers, Quants, and MLEs to analyze, optimize, and scale HPC workloads across CPU ... Work with platform teams to influence system design decisions based on real workload behavior and ...

IMC

HPC Engineer

Chicago, IL · On-site

$200K - $225K/yr

Partner with Researchers, Quants, and MLEs to analyze, optimize, and scale HPC workloads across CPU ... Work with platform teams to influence system design decisions based on real workload behavior and ...

Infleqtion

Senior Embedded Systems Engineer

Chicago, IL · On-site

$131K - $175K/yr

Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...

Infleqtion

Senior Embedded Systems Engineer

Chicago, IL

$131K - $175K/yr

Develop testable, performant, and scalable RTL using SpinalHDL. * Support hands on tuning and ... Participate in design, code, and data reviews. Requirements REQUIREMENTS * Bachelor's degree in ...

Databento

Software Engineer (C++/Rust)

Chicago, IL · On-site +1

... CPU cores at your disposal. Responsibilities * Design, develop, and maintain high-performance ... Knowledge of systems programming, algorithms, data structures, multithreading, networked I/O ...

iTech US, Inc.

Java Developer

Chicago Heights, IL · On-site

$49.75 - $64.25/hr

... design and support. Note: Some L3 support will be required over time for some components of the ... OS system - memory utilization, cpu utilization, disk i/o, system load etc.

Varite

Lead Golang Developer

Chicago, IL · On-site

$115K - $125K/yr

Design and implement low-latency services in Go for trading infrastructure and market data ... Engineer systems with deterministic execution, minimizing latency variance and tail latency.

Purple Drive

Performance Test Engineer

Chicago, IL · On-site

Design, develop, and execute performance, load, stress, spike, and endurance tests using Apache ... Response time * Throughput * CPU utilization * Memory utilization * Error rates * Good ...

DRW

Senior FPGA Engineer (Algo)

Chicago, IL · On-site

$150K - $250K/yr

Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ... Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing ...

Infleqtion

Senior Embedded Software Engineer

Chicago, IL

$127K - $167K/yr

The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...

Infleqtion

Senior Embedded Software Engineer

Chicago, IL · On-site

$127K - $167K/yr

The engineer will also serve as a point-of-contact (POC) for subsystem hardware integration with ... Design systems that meet deterministic latency, bandwidth, and reliability requirements across CPU ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Chicago, IL

Cpu Rtl Design Engineer information

See Chicago, IL salary details

$41.7K

$90.8K

$163.3K

How much do cpu rtl design engineer jobs pay per year?

As of Jun 30, 2026, the average yearly pay for cpu rtl design engineer in Chicago, IL is $90,807.00, according to ZipRecruiter salary data. Most workers in this role earn between $70,000.00 and $101,500.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Chicago, IL as of June 2026, with employment types broken down into 80% Full Time, 16% Part Time, 1% Temporary, and 3% Contract. Highlights an 90% Physical, 6% Hybrid, and 4% Remote job distribution, with an average salary of $90,807 per year, or $43.7 per hour.

HPC Engineer

IMC

Chicago, IL

Other

Posted 6 days ago

Key responsibilities

  • Partner with Researchers, Quants, and Machine Learning Engineers to analyze, optimize, and scale HPC workloads across CPU and GPU platforms.

  • Support and optimize machine learning and simulation workloads with a focus on performance, resource efficiency, and scalability.

  • Apply deep understanding of storage, networking, and scheduling systems to improve end-to-end workload performance.

Job description

At IMC, technology is not a department; it's at the heart of everything we do. Developed in-house, our systems power world-class research and trading, enabling teams to make faster and better decisions every day. Our high-performance computing platforms sit at the core of this capability, supporting large-scale simulation, research, and machine learning workloads across the firm.

We're looking for an HPC Engineer to work closely with Researchers, Machine Learning Engineers, and Software Engineers to get the most out of our compute platforms. This role is about applying deep systems and parallel computing expertise to help users get the best possible performance from modern CPU and GPU-based infrastructure.

Your Core Responsibilities:

As an HPC Engineer, you'll act as a technical partner to our compute users, helping translate computational problems into efficient, scalable workloads. You'll work across teams to improve performance, throughput, and reliability, while shaping best practices for how HPC resources are used across IMC.

  • Partner with Researchers, Quants, and MLEs to analyze, optimize, and scale HPC workloads across CPU and GPU platforms
  • Support and optimize ML and simulation workloads, with a focus on performance, resource efficiency, and scalability
  • Apply deep understanding of storage, networking, and scheduling systems to improve end-to-end workload performance
  • Define and promote best practices for running large-scale workloads on shared HPC infrastructure
  • Work with platform teams to influence system design decisions based on real workload behavior and performance data
  • Implement and use performance monitoring, profiling, and benchmarking tools to drive continuous improvement
  • Ensure workloads and platforms meet internal security and compliance standards

Your Skills and Experience

  • Experience working with HPC or large-scale compute environments, with a strong focus on workload performance and optimization
  • A solid grasp of parallel computing concepts and how to tune performance on CPUs and GPUs
  • Hands-on experience with GPU acceleration (e.g. CUDA) and an understanding of how GPU workloads really behave
  • Solid systems knowledge across Linux, storage and networking; enough to diagnose bottlenecks and guide users effectively
  • Experience supporting or optimizing ML, simulation, or data-intensive workloads in shared compute environments
  • Familiarity with containers and orchestration tools like Kubernetes is beneficial
  • Programming experience is advantageous, particularly in Python and C++
  • Strong communication skills and a genuine interest in helping others get better performance from complex systems
  • A high degree of flexibility and adaptability: willing and able to deal with uncertainty and ambiguity in a rapidly evolving environment

Apply