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Cpu Rtl Design Engineer Jobs in New York (NOW HIRING)

City of New York

Desktop Design Engineer

Brooklyn, NY · On-site

Responsibilities : • Provide Engineering Design level support of desktop and laptop computers and ... CPU and storage when needed; • Diagnose and document problem resolution, provide Root Cause ...

City of New York

Desktop Design Engineer

Brooklyn, NY · On-site

The Desktop Design Engineer is a key team member within the Enterprise Desktop Services Unit ... CPU and storage when needed; - Diagnose and document problem resolution, provide Root Cause ...

New

City of New York

Desktop Design Engineer

Brooklyn, NY · On-site

$100K - $125K/yr

The Desktop Design Engineer is a key team member within the Enterprise Desktop Services Unit ... CPU and storage when needed; -Diagnose and document problem resolution, provide Root Cause Analysis ...

Ciena Corporation

THW Client Co-op

New York, NY · On-site

$27 - $37.50/hr

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...

Ciena

THW Client Co-op

Manhattan, NY · On-site

$27 - $37.50/hr

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...

Normal Computing

Silicon Architect

New York, NY · On-site

$234K - $298K/yr

You have used cycle-accurate or analytical models to make and defend design decisions before RTL ... Experience writing microarchitecture specifications and working closely with RTL engineers through ...

Open Systems Technologies

C++ Developer

Manhattan, NY · On-site

$300K/yr

... a software engineer to help architect, design, and implement low latency C systems ... Understanding of CPU architecture with the ability to leverage CPU capabilities * Extensive ...

Qube Research & Technologies

FPGA Engineer

New York, NY

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

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Cpu Rtl Design Engineer information

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$44.3K

$96.4K

$173.4K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 15, 2026, the average yearly pay for cpu rtl design engineer in New York is $96,439.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,400.00 and $107,800.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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Cpu Rtl Design Engineer jobs near you
Hardware Engineer (FPGA/ASIC)

Hardware Engineer (FPGA/ASIC)

Jane Street

New York, NY

Other

Posted 4 days ago

Job description

About the Position

Our goal is to give you a real sense of what it's like to work at Jane Street full time while also providing a truly unparalleled educational experience. As an intern, you are paired with full-time employees who act as mentors, collaborating with you on real-world projects we actually need done.

In this internship, you'll learn how we use tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our hardware engineering work, and we're looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you'll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.

The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background and experience, we'll craft a project that gives you exposure to our shared Hardcaml tech stack, as well as targeting an FPGA or ASIC platform.

During the program, you'll dive deep on one project, mentored closely by the full-time employees who helped design it. Some intern projects consider big-picture questions that we're still trying to figure out, while others involve building something new. Your mentors will help you gain a better understanding of the wide range of problems we solve every day. We expect interns to build hardware applications from concept to a working design; your projects will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration.

If you'd like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode. You can also learn more about Jane Street's internship program here.

About You

We don't expect you to have a background in finance, OCaml, functional programming, or any other specific field- we're looking for smart people who enjoy solving interesting problems. We're more interested in how you think and learn than what you currently know. You should be:

  • Comfortable with a software programming language
  • Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
  • Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs
  • Experienced with building a working hardware project (either FPGA or ASIC) through an academic, professional, or personal project
  • Interested in learning how to use FPGAs or ASICs in the context of networking

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

Apply